參數(shù)資料
型號: SN74AHCT126QPWREP
廠商: TEXAS INSTRUMENTS INC
元件分類: 總線收發(fā)器
英文描述: AHCT/VHCT SERIES, QUAD 1-BIT DRIVER, TRUE OUTPUT, PDSO14
封裝: GREEN, PLASTIC, TSSOP-14
文件頁數(shù): 1/12頁
文件大?。?/td> 442K
代理商: SN74AHCT126QPWREP
SN74AHCT126EP
QUADRUPLE BUS BUFFER GATES
WITH 3STATE OUTPUTS
SCLS551 DECEMBER 2003
1
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
D Controlled Baseline
One Assembly/Test Site, One Fabrication
Site
D Extended Temperature Performance of
40
°C to 125°C
D Enhanced Diminishing Manufacturing
Sources (DMS) Support
D Enhanced Product-Change Notification
D Qualification Pedigree
Component qualification in accordance with JEDEC and industry
standards to ensure reliable operation over an extended
temperature range. This includes, but is not limited to, Highly
Accelerated Stress Test (HAST) or biased 85/85, temperature
cycle, autoclave or unbiased HAST, electromigration, bond
intermetallic life, and mold compound life. Such qualification
testing should not be viewed as justifying use of this component
beyond specified performance and environmental limits.
D ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF, R = 0)
D Inputs Are TTL-Voltage Compatible
description
The SN74AHCT126 device is a quadruple bus buffer gate featuring independent line drivers with 3-state
outputs. Each output is disabled when the associated output-enable (OE) input is low. When OE is high, the
respective gate passes the data from the A input to its Y output.
To ensure the high-impedance state during power up or power down, OE should be tied to GND through a
pulldown resistor; the minimum value of the resistor is determined by the current-sourcing capability of the
driver.
ORDERING INFORMATION
TA
PACKAGE
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
40
°C to 125°C
SOIC D
Tape and reel
SN74AHCT126QDREP
AHCT126QEP
40
°C to 125°C
TSSOP PW
Tape and reel
SN74AHCT126QPWREP
HB126EP
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are
available at www.ti.com/sc/package.
FUNCTION TABLE
(each buffer)
INPUTS
OUTPUT
OE
A
OUTPUT
Y
H
LL
L
X
Z
1
2
3
4
5
6
7
14
13
12
11
10
9
8
1OE
1A
1Y
2OE
2A
2Y
GND
VCC
4OE
4A
4Y
3OE
3A
3Y
D OR PW PACKAGE
(TOP VIEW)
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright
2003, Texas Instruments Incorporated
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
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