參數(shù)資料
型號(hào)： SN65LVDS390DG4
廠商： Texas Instruments
文件頁(yè)數(shù)： 3/28頁(yè)
文件大?。?/td> 0K
描述： IC DIFF LINE RECEIVER HS 16-SOIC
標(biāo)準(zhǔn)包裝： 40
系列： 65LVDS
類型： 線路接收器
驅(qū)動(dòng)器/接收器數(shù)： 0/4
規(guī)程： LVDS
電源電壓： 3 V ~ 3.6 V
安裝類型： 表面貼裝
封裝/外殼： 16-SOIC（0.154"，3.90mm 寬）
供應(yīng)商設(shè)備封裝： 16-SOIC N
包裝： 管件
Host
Controller
TX Clock
LVDS Drivers
Target
Controller
Target
Indicates twisting of the
conductors.
T
Indicates the line termination
circuit.
Host
Balanced Interconnect
Power
DB0
DB1
DB2
DBn–3
T
DBn–2
DBn–1
DBn
RX Clock
DB0
DB1
DB2
DBn–3
DBn–2
DBn–1
DBn
LVDx368, LVDx388
LVDx388A, or LVDx390
SLLS394H – SEPTEMBER 1999 – REVISED MAY 2007
APPLICATION INFORMATION
Figure 12. Typical Application Schematic
ANALOG AND DIGITAL GROUNDS/POWER SUPPLIES
Although it is not necessary to separate out the analog/digital supplies and grounds on the SN65LVDS/T388A
and SN75LVDS/T388A, the pinout provides the user that option. To help minimize or perhaps eliminate switching
noise being coupled between the two supplies, the user could lay out separate supply and ground planes for the
designated pinout.
Most applications probably have all grounds connected together and all power supplies connected together. This
configuration was used while characterizing and setting the data-sheet parameters.
FAIL SAFE
One of the most common problems with differential signaling applications is how the system responds when no
differential voltage is present on the signal pair. The LVDS receiver is like most differential line receivers, in that
its output logic state can be indeterminate when the differential input voltage is between –100 mV and 100 mV,
and within its recommended input common-mode voltage range. TI's LVDS receiver is different in how it handles
the open-input circuit situation, however.
Open-circuit means that there is little or no input current to the receiver from the data line itself. This could be
when the driver is in a high-impedance state or the cable is disconnected. When this occurs, the LVDS receiver
pulls each line of the signal pair to near VCC through 300-k resistors, as shown in Figure 13. The fail-safe
feature uses an AND gate with input voltage thresholds at about 2.3 V to detect this condition and force the
output to a high-level, regardless of the differential input voltage.
Copyright 1999–2007, Texas Instruments Incorporated
11
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SN65LVDS390DR 功能描述:LVDS 接口集成電路 QUAD LVDS RECEIVER RoHS:否 制造商:Texas Instruments 激勵(lì)器數(shù)量:4 接收機(jī)數(shù)量:4 數(shù)據(jù)速率:155.5 Mbps 工作電源電壓:5 V 最大功率耗散:1025 mW 最大工作溫度:+ 85 C 封裝 / 箱體:SOIC-16 Narrow 封裝:Reel
SN65LVDS390DRG4 功能描述:LVDS 接口集成電路 QUAD LVDS RECEIVER RoHS:否 制造商:Texas Instruments 激勵(lì)器數(shù)量:4 接收機(jī)數(shù)量:4 數(shù)據(jù)速率:155.5 Mbps 工作電源電壓:5 V 最大功率耗散:1025 mW 最大工作溫度:+ 85 C 封裝 / 箱體:SOIC-16 Narrow 封裝:Reel
SN65LVDS390PW 功能描述:LVDS 接口集成電路 Quad LVDS Rec RoHS:否 制造商:Texas Instruments 激勵(lì)器數(shù)量:4 接收機(jī)數(shù)量:4 數(shù)據(jù)速率:155.5 Mbps 工作電源電壓:5 V 最大功率耗散:1025 mW 最大工作溫度:+ 85 C 封裝 / 箱體:SOIC-16 Narrow 封裝:Reel
SN65LVDS390PWG4 功能描述:LVDS 接口集成電路 QUAD LVDS RECEIVER RoHS:否 制造商:Texas Instruments 激勵(lì)器數(shù)量:4 接收機(jī)數(shù)量:4 數(shù)據(jù)速率:155.5 Mbps 工作電源電壓:5 V 最大功率耗散:1025 mW 最大工作溫度:+ 85 C 封裝 / 箱體:SOIC-16 Narrow 封裝:Reel
SN65LVDS390PWR 功能描述:LVDS 接口集成電路 QUAD LVDS RECEIVER RoHS:否 制造商:Texas Instruments 激勵(lì)器數(shù)量:4 接收機(jī)數(shù)量:4 數(shù)據(jù)速率:155.5 Mbps 工作電源電壓:5 V 最大功率耗散:1025 mW 最大工作溫度:+ 85 C 封裝 / 箱體:SOIC-16 Narrow 封裝:Reel
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