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參數(shù)資料
| 型號： | SN65HVD56DG4 |
| 廠商： | Texas Instruments, Inc. |
| 元件分類： | RS-485 |
| 英文描述： | HIGH OUTPUT FULL-DUPLEX RS-485 DRIVERS AND RECEIVERS |
| 中文描述： | 高輸出全雙工RS - 485驅(qū)動器和接收 |
| 文件頁數(shù)： | 12/23頁 |
| 文件大小： | 1547K |
| 代理商： | SN65HVD56DG4 |
www.ti.com
B
A
R
V
O
V
I
V
O
t
PLH
t
PHL
50
W
V
I
Input
Generator
C =15pF
±20%
L
C
L
IncludesFixture
andInstrumentation
Capacitance
Generator
:
PRR
=
500
kHz
,
50
%
DutyCycle
,
t
<
6
ns
,
t
<
6
ns
,
Z
=
50
W
3
V
1
.
5
V
1
.
5
V
V
OH
V
OL
t
r
t
f
90
%
90
%
10
%
1
.
5
V
1
.
5
V
10
%
1.5V
0
V
RE
0V
B
A
R
V
O
50
W
V
I
Input
Generator
C
L
=15
pF
±20%
C
L
IncludesFixtureand
InstrumentationCapacitance
S1
1k
±1%
W
A
B
V
CC
V
I
t
PZH(1&2)
3V
1.5V
1.5V
PHZ
0V
V
O
1.5V
~0V
V
OH
0.5V
1.5V
0V
Generator:P
=500kHz,50%,DutyCycle,t <6ns,t <6ns,Z =50
RR
r
f
0
W
B
A
R
V
O
50
W
V
I
Input
Generator
C
L
=15
pF
±20%
C
L
IncludesFixture
andInstrumentation
Capacitance
Generator:P
=500kHz,50%,DutyCycle,t <6ns,t <6ns,Z =50
RR
r
f
0
W
RE
S1
1k
±1%
W
A
V
CC
B
V
V
O
3V
1.5V
1.5V
V
CC
V
OL
0.5V
0V
1.5V
t
PZL(1&2)
t
PLZ
0V
1.5V
SN65HVD50-SN65HVD55
SN65HVD56-SN65HVD59
SLLS666–SEPTEMBER 2005
PARAMETER MEASUREMENT INFORMATION (continued)
Figure 9. Receiver Switching Test Circuit and Voltage Waveforms
Figure 10. Receiver High-Level Enable and Disable Time Test Circuit and Voltage Waveforms
Figure 11. Receiver Low-Level Enable and Disable Time Test Circuit and Voltage Waveforms
12
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