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參數(shù)資料
| 型號： | SN54S374FK |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 總線收發(fā)器 |
| 英文描述： | S SERIES, 8-BIT DRIVER, TRUE OUTPUT, CQCC20 |
| 文件頁數(shù)： | 2/11頁 |
| 文件大?。?/td> | 394K |
| 代理商： | SN54S374FK |
PRODUCT FOLDER | PRODUCT INFO: FEATURES | DESCRIPTION | DATASHEETS | PRICING/AVAILABILITY | APPLICATION NOTES |
PRODUCT SUPPORT: TRAINING
SN54LS373, Octal D-type Transparent Latches And Edge-Triggered Flip-Flops with 3-state
Outputs
DEVICE STATUS: ACTIVE
PARAMETER NAME SN54LS373
Voltage Nodes (V) 5
Vcc range (V)
4.5 to 5.5
Input Level
TTL
Output Level
TTL
No. of Outputs
8
Logic
True
FEATURES
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Choice of 8 Latches or 8 D-Type Flip-Flops In a Single Package
q
3-State Bus-Driving Outputs
q
Full Parallel-Access for Loading
q
Buffered Control Inputs
q
Clock/Enable Input Has Hysteresis to Improve Noise Rejection ('S373 and 'S374)
q
P-N-P Inputs Reduce D-C Loading on Data Lines ('S373 and 'S374)
q
DESCRIPTION
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These 8-bit registers feature three-state outputs designed specifically for driving highly-capacitive or
relatively low-impedance loads. The high-impedance third state and increased high-logic-level drive provide
these registers with the capability of being connected directly to and driving the bus lines in a bus-organized
system without need for interface or pull-up components. They are particularly attractive for implementing
buffer registers, I/O ports, bidirectional bus drivers, and working registers.
The eight latches of the 'LS373 and 'S373 are transparent D-type latches meaning that while the enable (C)
is high the Q outputs will follow the data (D) inputs. When the enable is taken low the output will be latched
at the level of the data that was set up.
The eight flip-flops of the 'LS374 and 'S374 are edge-triggered D-type flip-flops. On the positive transition of
the clock, the Q outputs will be set to the logic states that were setup at the D inputs.
Schmitt-trigger buffered inputs at the enable/clock lines of the 'S373 and 'S374 devices, simplify system
design as ac and dc noise rejection is improved by typically 400 mV due to the input hysteresis. A buffered
output control input can be used to place the eight outputs in either a normal logic state (high or low logic
levels) or a high-impedance state. In the high-impedance state the outputs neither load nor drive the bus
lines significantly.
Product Folder:SN54LS373, Octal D-type Transparent Latches And Edge-Triggered Flip-Flops with 3-state Outputs
file:////roarer/root/export/projects/bitting1/imagin...Avnet/20001221/11092000/TXII/11092000/sn54ls373.html (1 of 2) [1/3/2001 11:22:19 AM]
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| SN54S374J | 制造商:Texas Instruments 功能描述:Flip Flop D-Type Bus Interface Pos-Edge 3-ST 1-Element 20-Pin CDIP Tube |
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