參數(shù)資料
型號(hào): SN54LVTH573FK
廠商: TEXAS INSTRUMENTS INC
元件分類: 總線收發(fā)器
英文描述: LVT SERIES, 8-BIT DRIVER, TRUE OUTPUT, CQCC20
封裝: CERAMIC, LCC-20
文件頁(yè)數(shù): 10/11頁(yè)
文件大小: 201K
代理商: SN54LVTH573FK
Product Folder: SN74LVTH573, 3.3-V ABT Octal Transparent D-Type Latches With 3-State Outputs
PRODUCT SUPPORT: TRAINING
SN74LVTH573, 3.3-V ABT Octal Transparent D-Type Latches With 3-State Outputs
DEVICE STATUS: ACTIVE
PARAMETER NAME SN54LVTH573 SN74LVTH573
Voltage Nodes (V) 3.3, 2.7
3.3, 2.7
Vcc range (V)
2.7 to 3.6
Output Drive (mA) -24/48
Static Current
5 mA
th (ns)
1.5
tpd max (ns)
4.5
tsu (ns)
0.7
FEATURES
q
Support Mixed-Mode Signal Operation (5-V Input and Output Voltages With 3.3-V VCC)
q
Support Unregulated Battery Operation Down to 2.7 V
q
Typical VOLP (Output Ground Bounce)
<0.8 V at VCC = 3.3 V, TA = 25°C
q
I off and Power-Up 3-State Support Hot Insertion
q
Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors
q
Latch-Up Performance Exceeds 500 mA Per JESD 17
q
ESD Protection Exceeds JESD 22
r
2000-V Human-Body Model (A114-A)
r
200-V Machine Model (A115-A)
DESCRIPTION
These octal latches are designed specifically for low-voltage (3.3-V) VCC operation, but with the capability to provide a TTL interface to a 5-V system environment.
The eight latches of the ’LVTH573 devices are transparent D-type latches. While the latch-enable (LE) input is high, the Q outputs follow the data (D) inputs. When LE is taken low, the Q outputs
are latched at the logic levels set up at the D inputs.
A buffered output-enable (OE\) input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or a high-impedance state. In the high-impedance state, the
outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without need for interface or pullup components.
OE does not affect the internal operations of the latches. Old data can be retained or new data can be entered while the outputs are in the high-impedance state.
When VCC is between 0 and 1.5 V, the devices are in the high-impedance state during power up or power down. However, to ensure the high-impedance state above 1.5 V, OE\ should be tied to
VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
file:///H|/imaging/BITTING/cpl/20020930_1/09272002_10/TXII/09272002_HTML/sn74lvth573.html (1 of 4) [Oct-05-2002 11:56:48 AM]
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