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參數(shù)資料
| 型號(hào)： | SN54LVTH2952FK |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 總線收發(fā)器 |
| 英文描述： | LVT SERIES, 8-BIT REGISTERED TRANSCEIVER, TRUE OUTPUT, CQCC28 |
| 封裝： | CERAMIC, CC-28 |
| 文件頁(yè)數(shù)： | 11/11頁(yè) |
| 文件大?。?/td> | 220K |
| 代理商： | SN54LVTH2952FK |
Product Folder: SN74LVTH2952, 3.3-V ABT Octal Bus Transceivers And Registers With 3-State Outputs
PRODUCT FOLDER | PRODUCT INFO: FEATURES | DESCRIPTION | DATASHEETS | PRICING/AVAILABILITY/PKG | SAMPLES
PRODUCT SUPPORT: TRAINING
SN74LVTH2952, 3.3-V ABT Octal Bus Transceivers And Registers With 3-State Outputs
DEVICE STATUS: ACTIVE
PARAMETER NAME SN74LVTH2952
Voltage Nodes (V) 3.3, 2.7
FEATURES
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State-of-the-Art Advanced BiCMOS Technology (ABT) Design for 3.3-V Operation and Low Static-Power Dissipation
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Ioff and Power-Up 3-State Support Hot Insertion
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Bus-Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors
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Support Mixed-Mode Signal Operation (5-V Input and Output Voltages With 3.3-V VCC)
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Support Unregulated Battery Operation Down to 2.7 V
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Typical VOLP (Output Ground Bounce) < 0.8 V at VCC = 3.3 V, TA = 25°C
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Latch-Up Performance Exceeds 500 mA Per JESD 17
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ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0)
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Package Options Include Plastic Small-Outline (DW), Shrink Small-Outline (DB), Thin Shrink Small-Outline (PW), and Thin Very Small-Outline (DGV) Packages, Ceramic Chip Carriers (FK),
and Ceramic (JT) DIPs
DESCRIPTION
These octal bus transceivers and registers are designed specifically for low-voltage (3.3-V) VCC operation, but with the capability to provide a TTL interface to a 5-V system environment.
The 'LVTH2952 devices consist of two 8-bit back-to-back registers that store data flowing in both directions between two bidirectional buses. Data on the A or B bus is stored in the registers on the
low-to-high transition of the clock (CLKAB or CLKBA) input, provided that the clock-enable (CLKENAB\ or CLKENBA\) input is low. Taking the output-enable (OEAB\ or OEBA\) input low accesses
the data on either port.
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.
When VCC is between 0 and 1.5 V, the devices are in the high-impedance state during power up or power down. However, to ensure the high-impedance state above 1.5 V, OE\ should be tied to
VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
These devices are fully specified for hot-insertion applications using Ioff and power-up 3-state. The Ioff circuitry disables the outputs, preventing damaging current backflow through the devices
when they are powered down. The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down, which prevents driver conflict.
The SN54LVTH2952 is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74LVTH2952 is characterized for operation from -40°C to 85°C.
TECHNICAL DOCUMENTS
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DATASHEET
file:///H|/imaging/BITTING/cpl/20020930_1/09272002_10/TXII/09272002_HTML/sn74lvth2952.html (1 of 3) [Oct-05-2002 11:54:23 AM]
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