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參數(shù)資料
| 型號： | SN54LVTH182502AHV |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 總線收發(fā)器 |
| 英文描述： | LVT SERIES, DUAL 9-BIT BOUNDARY SCAN REG TRANSCEIVER, TRUE OUTPUT, CQFP68 |
| 封裝： | CERAMIC, QFP-68 |
| 文件頁數(shù)： | 36/38頁 |
| 文件大?。?/td> | 556K |
| 代理商： | SN54LVTH182502AHV |
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SN54LVTH18502A, SN54LVTH182502A, SN74LVTH18502A, SN74LVTH182502A
3.3-V ABT SCAN TEST DEVICES
WITH 18-BIT UNIVERSAL BUS TRANSCEIVERS
SCBS668B – JULY 1996 – REVISED MARCH 1999
7
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
state diagram description
The TAP controller is a synchronous finite-state machine that provides test control signals throughout the
device. The state diagram shown in Figure 1 is in accordance with IEEE Standard 1149.1-1990. The TAP
controller proceeds through its states based on the level of TMS at the rising edge of TCK.
As shown, the TAP controller consists of 16 states. There are six stable states (indicated by a looping arrow in
the state diagram) and ten unstable states. A stable state is a state the TAP controller can retain for consecutive
TCK cycles. Any state that does not meet this criterion is an unstable state.
There are two main paths through the state diagram: one to access and control the selected data register and
one to access and control the instruction register. Only one register can be accessed at a time.
Test-Logic-Reset
The device powers up in the Test-Logic-Reset state. In the stable Test-Logic-Reset state, the test logic is reset
and is disabled so that the normal logic function of the device is performed. The instruction register is reset to
an opcode that selects the optional IDCODE instruction, if supported, or the BYPASS instruction. Certain data
registers can also be reset to their power-up values.
The state machine is constructed such that the TAP controller returns to the Test-Logic-Reset state in no more
than five TCK cycles if TMS is left high. The TMS pin has an internal pullup resistor that forces it high if left
unconnected or if a board defect causes it to be open circuited.
For the ’LVTH18502A and ’LVTH182502A, the instruction register is reset to the binary value 10000001, which
selects the IDCODE instruction. Bits 47–44 in the boundary-scan register are reset to logic 1, ensuring that
these cells, which control A-port and B-port outputs, are set to benign values (i.e., if test mode were invoked
the outputs would be at the high-impedance state). Reset-value of other bits in the boundary-scan register
should be considered indeterminate. The boundary-control register is reset to the binary value 010, which
selects the PSA test operation.
Run-Test/Idle
The TAP controller must pass through the Run-Test /Idle state (from Test-Logic-Reset) before executing any test
operations. The Run-Test /Idle state also can be entered following data-register or instruction-register scans.
Run-Test/Idle is a stable state in which the test logic can be actively running a test or can be idle. The test
operations selected by the boundary-control register are performed while the TAP controller is in the
Run-Test /Idle state.
Select-DR-Scan, Select-lR-Scan
No specific function is performed in the Select-DR-Scan and Select-lR-Scan states, and the TAP controller exits
either of these states on the next TCK cycle. These states allow the selection of either data-register scan or
instruction-register scan.
Capture-DR
When a data-register scan is selected, the TAP controller must pass through the Capture-DR state. In the
Capture-DR state, the selected data register can capture a data value as specified by the current instruction.
Such capture operations occur on the rising edge of TCK, upon which the TAP controller exits the
Capture-DR state.
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