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參數(shù)資料
| 型號： | SN54LVTH126FK |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 總線收發(fā)器 |
| 英文描述： | LVT SERIES, QUAD 1-BIT DRIVER, TRUE OUTPUT, CQCC20 |
| 封裝： | CERAMIC, LCC-20 |
| 文件頁數(shù)： | 1/7頁 |
| 文件大小： | 108K |
| 代理商： | SN54LVTH126FK |
SN54LVTH126, SN74LVTH126
3.3-V ABT QUADRUPLE BUS BUFFERS
WITH 3-STATE OUTPUTS
SCBS746 – JULY 2000
1
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
D State-of-the-Art Advanced BiCMOS
Technology (ABT) Design for 3.3-V
Operation and Low Static-Power
Dissipation
D Support Mixed-Mode Signal Operation (5-V
Input and Output Voltages With 3.3-V VCC)
D Support Unregulated Battery Operation
Down to 2.7 V
D Typical VOLP (Output Ground Bounce)
<0.8 V at VCC = 3.3 V, TA = 25°C
D Ioff and Power-Up 3-State Support Hot
Insertion
D Bus Hold on Data Inputs Eliminates the
Need for External Pullup/Pulldown
Resistors
D Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
D ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
D Package Options Include Plastic
Small-Outline (D), Shrink Small-Outline
(DB), Thin Very Small-Outline (DGV), and
Thin Shrink Small-Outline (PW), and
Ceramic Flat (W) Packages, Ceramic Chip
Carriers (FK), and Ceramic (J) DIPs
description
These bus buffers are designed specifically for low-voltage (3.3-V) VCC operation, but with the capability to
provide a TTL interface to a 5-V system environment.
The ’LVTH126 devices feature independent line drivers with 3-state outputs. Each output is in the
high-impedance state when the associated output-enable (OE) input is low.
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.
When VCC is between 0 and 1.5 V, the device is in the high-impedance state during power up or power down.
However, to ensure the high-impedance state above 1.5 V, OE should be tied to GND through a pulldown
resistor; the minimum value of the resistor is determined by the current-sourcing capability of the driver.
These devices are fully specified for hot-insertion applications using Ioff and power-up 3-state. The Ioff circuitry
disables the outputs, preventing damaging current backflow through the devices when they are powered down.
The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down,
which prevents driver conflict.
Copyright
2000, Texas Instruments Incorporated
UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
SN54LVTH126 ...J OR W PACKAGE
SN74LVTH126 . . . D, DB, DGV, OR PW PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
14
13
12
11
10
9
8
1OE
1A
1Y
2OE
2A
2Y
GND
VCC
4OE
4A
4Y
3OE
3A
3Y
32
1 20 19
910 11 12 13
4
5
6
7
8
18
17
16
15
14
4A
NC
4Y
NC
3OE
1Y
NC
2OE
NC
2A
1A
1OE
NC
3Y
3A
V
4OE
2Y
GND
NC
CC
NC – No internal connection
SN54LVTH126 . . . FK PACKAGE
(TOP VIEW)
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