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參數(shù)資料
| 型號(hào)： | SN54LV221AJ |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 諧振器 |
| 英文描述： | LV/LV-A/LVX/H SERIES, DUAL MONOSTABLE MULTIVIBRATOR, CDIP16 |
| 封裝： | CERAMIC, DIP-16 |
| 文件頁(yè)數(shù)： | 6/13頁(yè) |
| 文件大?。?/td> | 213K |
| 代理商： | SN54LV221AJ |
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SN54LV221A, SN74LV221A
DUAL MONOSTABLE MULTIVIBRATORS
WITH SCHMITT-TRIGGER INPUTS
SCLS450B – DECEMBER 1999 – REVISED AUGUST 2000
2
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
description (continued)
Once triggered, the outputs are independent of further transitions of the A and B inputs and are a function of
the timing components, or the output pulses can be terminated by the overriding clear. Input pulses may be of
any duration relative to the output pulse. Output pulse duration can be varied by choosing the appropriate timing
components. Output rise and fall times are TTL compatible and independent of pulse duration. Typical triggering
and clearing sequences are illustrated in the input/output timing diagram.
The variance in output pulse duration from device to device typically is less than
±0.5% for given external timing
components. An example of this distribution for the ’LV221A is shown in Figure 8. Variations in output pulse
duration versus supply voltage and temperature are shown in Figure 5.
During power up, Q outputs are in the low state, and Q outputs are in the high state. The outputs are glitch free,
without applying a reset pulse.
Pin assignments are identical to those of the ’AHC123A and ’AHCT123A devices, so the ’LV221A can be
substituted for those devices not using the retrigger feature.
The SN54LV221A is characterized for operation over the full military temperature range of –55
°C to 125°C.
The SN74LV221A is characterized for operation from –40
°C to 85°C.
For additional application information on multivibrators, see the application report
Designing With The
SN74AHC123A and SN74AHCT123A, literature number SCLA014.
FUNCTION TABLE
(each multivibrator)
INPUTS
OUTPUTS
FUNCTION
CLR
A
B
Q
FUNCTION
L
X
L
H
Reset
H
HX
L
H
Inhibit
H
XL
L
H
Inhibit
H
L
↑
Outputs enabled
H
#
H
Outputs enabled
↑
L
H
Outputs enabled
This condition is true only if the output of the latch formed by the
NAND gate has been conditioned to the logic 1 state prior to CLR
going high. This latch is conditioned by taking either A high or B
low while CLR is inactive (high).
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