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參數(shù)資料
| 型號(hào)： | SN54LV174AFK |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 鎖存器 |
| 英文描述： | LV/LV-A/LVX/H SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, CQCC20 |
| 封裝： | CERAMIC, LCC-20 |
| 文件頁(yè)數(shù)： | 7/11頁(yè) |
| 文件大小： | 199K |
| 代理商： | SN54LV174AFK |
SN54LV174A, SN74LV174A
HEX D-TYPE FLIP-FLOPS
WITH CLEAR
SCLS401C – APRIL 1998 – REVISED MAY 2000
5
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
timing requirements over recommended operating free-air temperature range, VCC = 2.5 V ± 0.2 V
(unless otherwise noted) (see Figure 1)
TA = 25°C
SN54LV174A
SN74LV174A
UNIT
MIN
TYP
MAX
MIN
MAX
MIN
MAX
UNIT
t
Pulse duration
CLR low
6
6.5
ns
tw
Pulse duration
CLK high or low
7
ns
t
Set p time before CLK
↑
Data
8.5
9.5
ns
tsu
Setup time before CLK
↑
CLR inactive
4
ns
th
Hold time, data after CLK
↑
–0.5
0
ns
timing requirements over recommended operating free-air temperature range, VCC = 3.3 V ± 0.3 V
(unless otherwise noted) (see Figure 1)
TA = 25°C
SN54LV174A
SN74LV174A
UNIT
MIN
TYP
MAX
MIN
MAX
MIN
MAX
UNIT
t
Pulse duration
CLR low
5
ns
tw
Pulse duration
CLK high or low
5
ns
t
Set p time before CLK
↑
Data
5
6
ns
tsu
Setup time before CLK
↑
CLR inactive
3
ns
th
Hold time, data after CLK
↑
0
ns
timing requirements over recommended operating free-air temperature range, VCC = 5 V ± 0.5 V
(unless otherwise noted) (see Figure 1)
TA = 25°C
SN54LV174A
SN74LV174A
UNIT
MIN
TYP
MAX
MIN
MAX
MIN
MAX
UNIT
t
Pulse duration
CLR low
5
ns
tw
Pulse duration
CLK high or low
5
ns
t
Set p time before CLK
↑
Data
4.5
ns
tsu
Setup time before CLK
↑
CLR inactive
2.5
ns
th
Hold time, data after CLK
↑
0.5
ns
switching characteristics over recommended operating free-air temperature range,
VCC = 2.5 V ± 0.2 V (unless otherwise noted) (see Figure 1)
PARAMETER
FROM
TO
LOAD
TA = 25°C
SN54LV174A
SN74LV174A
UNIT
PARAMETER
(INPUT)
(OUTPUT)
CAPACITANCE
MIN
TYP
MAX
MIN
MAX
MIN
MAX
UNIT
f
CL = 15 pF
55*
115*
50*
50
MHz
fmax
CL = 50 pF
45
90
40
MHz
tpd
CLR
Q
CL =15 pF
6.3*
17.3*
1*
19.5*
1
19.5
ns
tpd
CLK
Q
CL = 15 pF
8.4*
17.1*
1*
19*
1
19
ns
tpd
CLR
Q
8.2
21.9
1
23.5
1
23.5
tpd
CLK
Q
CL = 50 pF
10.8
20.6
1
23
1
23
ns
tsk(o)
2
* On products compliant to MIL-PRF-38535, this parameter is not production tested.
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
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