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參數(shù)資料
| 型號： | SN54LV165AFK |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 計數(shù)移位寄存器 |
| 英文描述： | LV/LV-A/LVX/H SERIES, 8-BIT RIGHT PARALLEL IN SERIAL OUT SHIFT REGISTER, COMPLEMENTARY OUTPUT, CQCC20 |
| 封裝： | CERAMIC, LCC-20 |
| 文件頁數(shù)： | 11/11頁 |
| 文件大?。?/td> | 210K |
| 代理商： | SN54LV165AFK |
SN74LV165A, Parallel-Load 8-Bit Shift Registers
DEVICE STATUS: ACTIVE
l
EPICTM
(Enhanced-Performance Implanted CMOS) Process
l
2-V to 5.5-V V
CC
Operation
l Support Mixed-Mode Voltage Operation on All Ports
l
Latch-Up Performance Exceeds 250 mA Per JESD 17
l
ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using
Machine Model (C = 200 pF, R = 0)
l
Package Options Include Plastic Small-Outline (D, NS), Shrink Small-Outline (DB), Thin
Very Small-Outline (DGV), and Thin Shrink Small-Outline (PW) Packages, Ceramic Flat
(W) Packages, Chip Carriers (FK), and DIPs (J)
EPIC is a trademark of Texas Instruments.
The 'LV165A devices are parallel-load, 8-bit shift registers designed for 2-V to 5.5-V V
CC
operation.
When the device is clocked, data is shifted toward the serial output Q
H. Parallel-in access to
each stage is provided by eight individual direct data inputs that are enabled by a low level at
the shift/load (SH/LD\) input. The 'LV165A devices feature a clock inhibit function and a
complemented serial output Q\
H
.
Clocking is accomplished by a low-to-high transition of the clock (CLK) input while SH/LD\ is
held high and clock inhibit (CLK INH) is held low.
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MODELS
PRODUCT SUPPORT: TRAINING
PARAMETER NAME SN74LV165A
Voltage Nodes (V) 5, 3.3, 2.5
FEATURES
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