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參數(shù)資料
| 型號(hào)： | SN54LS95J |
| 廠商： | Motorola, Inc. |
| 英文描述： | Single 2 Input AND Gate; Package: TSOP-5 / SOT23-5; No of Pins: 5; Container: Tape and Reel; Qty per Container: 3000 |
| 中文描述： | 4位移位寄存器 |
| 文件頁數(shù)： | 4/6頁 |
| 文件大小： | 200K |
| 代理商： | SN54LS95J |
5-174
FAST AND LS TTL DATA
SN54/74LS95B
DESCRIPTION OF TERMS
SETUP TIME(ts) —is defined as the minimum time required
for the correct logic level to be present at the logic input prior to
the clock transition from HIGH to LOW in order to be recog-
nized and transferred to the outputs.
HOLD TIME (th) — is defined as the minimum time following
the clock transition from HIGH to LOW that the logic level must
be maintained at the input in order to ensure continued recog-
nition. A negative HOLD TIME indicates that the correct logic
level may be released prior to the clock transition from HIGH to
LOW and still be recognized.
AC WAVEFORMS
Figure 1
Figure 2
The shaded areas indicate when the input is permitted to change for predictable output performance.
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*The Data Input is
(DS for CP1) or (Pn for CP2).
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