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參數(shù)資料
| 型號： | SN54LS379J |
| 廠商： | MOTOROLA INC |
| 元件分類： | 通用總線功能 |
| 英文描述： | Quad 2-Input AND Gate; Package: PDIP-14; No of Pins: 14; Container: Tube; Qty per Container: 500 |
| 中文描述： | LS SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, CDIP16 |
| 封裝： | CERAMIC, DIP-16 |
| 文件頁數(shù)： | 4/7頁 |
| 文件大?。?/td> | 250K |
| 代理商： | SN54LS379J |
5-536
FAST AND LS TTL DATA
SN54/74LS377
SN54/74LS378
SN54/74LS379
GUARANTEED OPERATING RANGES
Symbol
VCC
Parameter
Min
4.5
4.75
Typ
5.0
5.0
Max
5.5
5.25
Unit
V
Supply Voltage
54
74
TA
Operating Ambient Temperature Range
54
74
–55
0
25
25
125
70
°
C
IOH
IOL
Output Current — High
54, 74
–0.4
mA
Output Current — Low
54
74
4.0
8.0
mA
DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE
(unless otherwise specified)
Symbol
Parameter
Limits
Typ
Unit
Test Conditions
Min
Max
VIH
Input HIGH Voltage
2.0
V
Guaranteed Input HIGH Voltage for
All Inputs
VIL
Input LOW Voltage
54
0.7
V
Guaranteed Input LOW Voltage for
All Inputs
74
0.8
VIK
Input Clamp Diode Voltage
–0.65
–1.5
V
VCC = MIN, IIN = –18 mA
or VIL per Truth Table
VOH
Output HIGH Voltage
54
2.5
3.5
V
74
2.7
3.5
V
VCC = MIN, IOH = MAX, VIN = VIH
VOL
Output LOW Voltage
54, 74
0.25
0.4
V
IOL = 4.0 mA
VCC = VCC MIN,
per Truth Table
74
0.35
0.5
V
IOL = 8.0 mA
VCC = MAX, VIN = 2.7 V
VCC = MAX, VIN = 7.0 V
VCC = MAX, VIN = 0.4 V
VCC = MAX
VIN = VIL or VIH
IIH
Input HIGH Current
20
μ
A
mA
0.1
IIL
IOS
Input LOW Current
–0.4
mA
Short Circuit Current (Note 1)
–20
–100
mA
ICC
Power Supply Current
LS377
LS378
LS379
28
22
15
mA
VCC = MAX, NOTE 1
NOTE: With all inputs open and GND applied to all data and enable inputs, ICC is measured after a momentary GND, then 4.5 V is applied to clock.
Note 1: Not more than one output should be shorted at a time, nor for more than 1 second.
AC CHARACTERISTICS
(TA = 25
°
C, VCC = 5.0 V)
Symbol
Parameter
Limits
Unit
Test Conditions
Min
30
Typ
40
Max
fMAX
tPLH
tPHL
Maximum Clock Frequency
MHz
CL = 15 pF
Propagation Delay,
Clock to Output
17
18
27
27
ns
VCC = 5.0 V
AC SETUP REQUIREMENTS
(TA = 25
°
C, VCC = 5.0 V)
Symbol
tW
ts
Parameter
Limits
Unit
ns
Test Conditions
Min
20
Typ
Max
Any Pulse Width
VCC = 5.0 V
Data Setup Time
20
ns
ts
Enable Setup
Time
Inactive — State
10
ns
Active — State
25
ns
th
Any Hold Time
5.0
ns
DEFINITION OF TERMS
SETUP TIME (ts) — is defined as the minimum time required
for the correct logic level to be present at the logic input prior to
the clock transition from LOW-to-HIGH in order to be recog-
nized and transferred to the outputs.
HOLD TIME (th) — is defined as the minimum time following
the clock transition from LOW-to-HIGH that the logic level
must be maintained at the input in order to ensure continued
recognition. A negative HOLD TIME indicates that the correct
logic level may be released prior to the clock transition from
LOW-to-HIGH and still be recognized.
相關PDF資料 |
PDF描述 |
|---|---|
| SN74LS377N | OCTAL D FLIP-FLOP WITH ENABLE; HEX D FLIP-FLOP WITH ENABLE; 4-BIT D FLIP-FLOP WITH ENABLE |
| SN74LS378D | OCTAL D FLIP-FLOP WITH ENABLE; HEX D FLIP-FLOP WITH ENABLE; 4-BIT D FLIP-FLOP WITH ENABLE |
| SN74LS378DW | OCTAL D FLIP-FLOP WITH ENABLE; HEX D FLIP-FLOP WITH ENABLE; 4-BIT D FLIP-FLOP WITH ENABLE |
| SN74LS378N | OCTAL D FLIP-FLOP WITH ENABLE; HEX D FLIP-FLOP WITH ENABLE; 4-BIT D FLIP-FLOP WITH ENABLE |
| SN74LS379D | OCTAL D FLIP-FLOP WITH ENABLE; HEX D FLIP-FLOP WITH ENABLE; 4-BIT D FLIP-FLOP WITH ENABLE |
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