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參數(shù)資料
| 型號： | SN54LS374J |
| 廠商： | MOTOROLA INC |
| 元件分類： | 通用總線功能 |
| 英文描述： | Hex Inverter; Package: SOEIAJ-14; No of Pins: 14; Container: Rail; Qty per Container: 50 |
| 中文描述： | LS SERIES, 8-BIT DRIVER, TRUE OUTPUT, CDIP20 |
| 封裝： | CERAMIC, DIP-20 |
| 文件頁數(shù)： | 3/7頁 |
| 文件大?。?/td> | 250K |
| 代理商： | SN54LS374J |
5-523
FAST AND LS TTL DATA
SN54/74LS373
SN54/74LS374
DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE
(unless otherwise specified)
Symbol
Parameter
Limits
Unit
Test Conditions
Min
Typ
Max
VIH
Input HIGH Voltage
2.0
V
Guaranteed Input HIGH Voltage for
All Inputs
VIL
Input LOW Voltage
54
0.7
V
Guaranteed Input LOW Voltage for
All Inputs
74
0.8
VIK
Input Clamp Diode Voltage
–0.65
–1.5
V
VCC = MIN, IIN = –18 mA
VOH
Output HIGH Voltage
54
2.4
3.4
V
or VIL per Truth Table
74
2.4
3.1
V
VCC = MIN, IOH = MAX, VIN = VIH
VOL
Output LOW Voltage
54, 74
0.25
0.4
V
IOL = 12 mA
VCC = VCC MIN,
per Truth Table
74
0.35
0.5
V
IOL = 24 mA
VIN = VIL or VIH
IOZH
IOZL
Output Off Current HIGH
20
μ
A
VCC = MAX, VOUT = 2.7 V
VCC = MAX, VOUT = 0.4 V
VCC = MAX, VIN = 2.7 V
VCC = MAX, VIN = 7.0 V
VCC = MAX, VIN = 0.4 V
VCC = MAX
VCC = MAX
Output Off Current LOW
–20
μ
A
IIH
Input HIGH Current
20
μ
A
0.1
mA
IIL
IOS
ICC
Note 1: Not more than one output should be shorted at a time, nor for more than 1 second.
Input LOW Current
–0.4
mA
Short Circuit Current (Note 1)
–30
–130
mA
Power Supply Current
40
mA
AC CHARACTERISTICS
(TA = 25
°
C, VCC = 5.0 V)
Symbol
Parameter
Limits
Unit
Test Conditions
LS373
LS374
Min
Typ
Max
Min
Typ
Max
fMAX
tPLH
tPHL
Maximum Clock Frequency
35
50
MHz
RL = 667
Propagation Delay,
Data to Output
12
12
18
18
ns
CL = 45 pF,
tPLH
tPHL
Clock or Enable
to Output
20
18
30
30
15
19
28
28
ns
tPZH
tPZL
Output Enable Time
15
25
28
36
20
21
28
28
ns
tPHZ
tPLZ
Output Disable Time
12
15
20
25
12
15
20
25
ns
CL = 5.0 pF
AC SETUP REQUIREMENTS
(TA = 25
°
C, VCC = 5.0 V)
Symbol
Parameter
Limits
Unit
LS373
LS374
Min
Max
Min
Max
tW
ts
th
Clock Pulse Width
15
15
ns
Setup Time
5.0
20
ns
Hold Time
20
0
ns
DEFINITION OF TERMS
SETUP TIME (ts) — is defined as the minimum time required
for the correct logic level to be present at the logic input prior to
LE transition from HIGH-to-LOW in order to be recognized and
transferred to the outputs.
HOLD TIME (th) — is defined as the minimum time following
the LE transition from HIGH-to-LOW that the logic level must
be maintained at the input in order to ensure continued
recognition.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SN54LS374J/883B | 制造商:MMI 功能描述: |
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| SN54LS377WB | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| SN54LS378J | 制造商:Texas Instruments 功能描述:Flip Flop D-Type Bus Interface Pos-Edge 1-Element 16-Pin CDIP Tube |
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