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參數(shù)資料
| 型號： | SN54LS175W |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 鎖存器 |
| 英文描述： | LS SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, CDFP16 |
| 封裝： | CERAMIC, DFP-16 |
| 文件頁數(shù)： | 5/15頁 |
| 文件大小： | 490K |
| 代理商： | SN54LS175W |
Product Folder: SN74S175, Quadruple D-Type Flip-Flops With Clear
PRODUCT SUPPORT: TRAINING
SN74S175, Quadruple D-Type Flip-Flops With Clear
DEVICE STATUS: ACTIVE
PARAMETER NAME SN54S175 SN74S175
Voltage Nodes (V) 5
5
Vcc range (V)
4.5 to 5.5 4.75 to 5.25
Input Level
TTL
Output Level
TTL
Output Drive (mA)
-1/20
Output
2S
No. of Bits
4
Static Current
96
th (ns)
3
tpd max (ns)
17
tsu (ns)
5
FEATURES
q
'174, 'LS174, 'S174 Contain Six Flip-Flops with Single-Rail Outputs
q
'175, 'LS175, 'S175 Contain Four Flip-Flops with Double-Rail Outputs
q
Three Performance Ranges Offered: See Table Lower Right
q
Buffered Clock and Direct Clear Inputs
q
Individual Data Input to Each Flip-Flop
q
Applications include:
r
Buffer/Storage Registers
r
Shift Registers
r
Pattern Generators
DESCRIPTION
These monolithic, positive-edge-triggered flip-flops utilize TTL circuitry to implement D-type flip-flop logic. All have a direct clear input, and the '175, 'LS175, and 'S175 feature complementary
outputs from each flip-flop.
Information at the D inputs meeting the setup time requirements is transferred to the Q outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a particular voltage level
and is not directly related to the transition time of the positive-going pulse. When the clock input is at either the high or low level, the D input signal has no effect at the output.
These circuits are fully compatible for use with most TTL circuits.
TECHNICAL DOCUMENTS
To view the following documents, Acrobat Reader 4.0 is required.
file:///H|/imaging/BITTING/cpl/20020930_1/09272002_10/TXII/09272002_HTML/sn74s175.html (1 of 3) [Oct-05-2002 10:26:01 AM]
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