參數(shù)資料
型號(hào): SN54LS107J
廠商: Motorola, Inc.
英文描述: Quad 2-Input AND Gate; Package: SOIC 14 LEAD; No of Pins: 14; Container: Rail; Qty per Container: 55
中文描述: 雙JK負(fù)邊沿觸發(fā)器
文件頁數(shù): 2/4頁
文件大?。?/td> 128K
代理商: SN54LS107J
5-178
FAST AND LS TTL DATA
SN54/74LS107A
DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE
(unless otherwise specified)
Symbol
Parameter
Limits
Unit
Test Conditions
Min
Typ
Max
VIH
Input HIGH Voltage
2.0
V
Guaranteed Input HIGH Voltage for
All Inputs
VIL
Input LOW Voltage
54
0.7
V
Guaranteed Input LOW Voltage for
All Inputs
74
0.8
VIK
Input Clamp Diode Voltage
–0.65
–1.5
V
VCC = MIN, IIN = –18 mA
VOH
Output HIGH Voltage
54
2.5
3.5
V
or VIL per Truth Table
74
2.7
3.5
V
VCC = MIN, IOH = MAX, VIN = VIH
VOL
Output LOW Voltage
54, 74
0.25
0.4
V
IOL = 4.0 mA
VCC = VCC MIN,
per Truth Table
74
0.35
0.5
V
IOL = 8.0 mA
VIN = VIL or VIH
IIH
Input HIGH Current
J, K
Clear
Clock
20
60
80
μ
A
VCC = MAX, VIN = 2.7 V
J, K
Clear
Clock
0.1
0.3
0.4
mA
VCC = MAX, VIN = 7.0 V
IIL
Input LOW Current
J, K
Clear and Clock
–0.4
–0.8
mA
VCC = MAX, VIN = 0.4 V
IOS
ICC
Note 1: Not more than one output should be shorted at a time, nor for more than 1 second.
Short Circuit Current (Note 1)
–20
–100
mA
VCC = MAX
VCC = MAX
Power Supply Current
6.0
mA
AC CHARACTERISTICS
(TA = 25
°
C, VCC = 5.0 V)
Symbol
Parameter
Limits
Unit
Test Conditions
Min
Typ
Max
fMAX
Maximum Clock Frequency
30
45
MHz
CL = 15 pF
tPHL
Propagation Delay,
Clock to Output
15
20
ns
VCC = 5.0 V
tPLH
15
20
ns
AC SETUP REQUIREMENTS
(TA = 25
°
C, VCC = 5.0 V)
Symbol
Parameter
Limits
Unit
Test Conditions
Min
Typ
Max
tW
tW
ts
th
Clock Pulse Width
20
ns
VCC = 5.0 V
Clear Pulse Width
25
ns
Setup Time
20
ns
Hold Time
0
ns
相關(guān)PDF資料
PDF描述
SN74LS107N 500mA, 5V,±2% Tolerance, Voltage Regulator, Ta = -40°C to +125°C; Package: DPAK 4 LEAD Single Gauge Surface Mount; No of Pins: 4; Container: Rail; Qty per Container: 75
SN74LS11D TRIPLE 3-INPUT AND GATE
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