
SN54HCT646, SN74HCT646
OCTAL BUS TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUTPUTS
SCLS178C – MARCH 1984 – REVISED MARCH 2003
5
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
recommended operating conditions (see Note 4)
SN54HCT646
SN74HCT646
UNIT
MIN
NOM
MAX
MIN
NOM
MAX
UNIT
VCC
Supply voltage
4.5
5
5.5
4.5
5
5.5
V
VIH
High-level input voltage
VCC = 4.5 V to 5.5 V
2
V
VIL
Low-level input voltage
VCC = 4.5 V to 5.5 V
0.8
V
VI
Input voltage
0
VCC
0
VCC
V
VO
Output voltage
0
VCC
0
VCC
V
tt
Input transition (rise and fall) time
500
ns
TA
Operating free-air temperature
–55
125
–40
85
°C
NOTE 4: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
TA = 25°C
SN54HCT646
SN74HCT646
UNIT
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX
MIN
MAX
MIN
MAX
UNIT
VOH
VI =VIH or VIL
IOH = –20 A
45 V
4.4
4.499
4.4
V
VOH
VI = VIH or VIL
IOH = –6 mA
4.5 V
3.98
4.3
3.7
3.84
V
VOL
VI =VIH or VIL
IOL = 20 A
45 V
0.001
0.1
V
VOL
VI = VIH or VIL
IOL = 6 mA
4.5 V
0.17
0.26
0.4
0.33
V
II
Control inputs
VI = VCC or 0
5.5 V
±0.1
±100
±1000
nA
IOZ
A or B
VO = VCC or 0
5.5 V
±0.01
±0.5
±10
±5
A
ICC
VI = VCC or 0,
IO = 0
5.5 V
8
160
80
A
ICC
One input at 0.5 V or 2.4 V,
Other inputs at 0 or VCC
5.5 V
1.4
2.4
3
2.9
mA
Ci
Control inputs
4.5 V
to 5.5 V
3
10
pF
This is the increase in supply current for each input that is at one of the specified TTL voltage levels, rather than 0 V or VCC.
timing requirements over recommended operating free-air temperature range (unless otherwise
noted)
VCC
TA = 25°C
SN54HCT646
SN74HCT646
UNIT
VCC
MIN
MAX
MIN
MAX
MIN
MAX
UNIT
f lk
Clock frequency
4.5 V
31
22
27
MHz
fclock
Clock frequency
5.5 V
36
24
29
MHz
t
Pulse duration CLKBA or CLKAB high or low
4.5 V
16
23
19
ns
tw
Pulse duration, CLKBA or CLKAB high or low
5.5 V
14
21
17
ns
t
S t
ti
A b f
CLKAB
↑
B b f
CLKBA
↑
4.5 V
20
30
25
ns
tsu
Setup time, A before CLKAB
↑ or B before CLKBA↑
5.5 V
18
27
23
ns
th
Hold time A after CLKAB
↑ or B after CLKBA↑
4.5 V
5
ns
th
Hold time, A after CLKAB
↑ or B after CLKBA↑
5.5 V
5
ns
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.