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參數(shù)資料
| 型號： | SN54HC138W |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 編、解碼器及復用、解復用 |
| 英文描述： | HC/UH SERIES, OTHER DECODER/DRIVER, INVERTED OUTPUT, CDFP16 |
| 封裝： | CERAMIC, FP-16 |
| 文件頁數(shù)： | 10/12頁 |
| 文件大?。?/td> | 192K |
| 代理商： | SN54HC138W |
SN54HC138, 3-Line To 8-Line Decoders/Demultiplexers
DEVICE STATUS: ACTIVE
l
Designed Specifically for High-Speed Memory Decoders and Data Transmission Systems
l
Incorporate Three Enable Inputs to Simplify Cascading and/or Data Reception
l Package Options Include Plastic Small-Outline (D), Thin Shrink Small-Outline (PW), and
Ceramic Flat (W) Packages, Ceramic Chip Carriers (FK), and Standard Plastic (N) and
Ceramic (J) 300-mil DIPs
The 'HC138 are designed to be used in high-performance memory-decoding or data -routing
applications requiring very short propagation delay times. In high-performance memory
systems, these decoders can be used to minimize the effects of system decoding. When
employed with high-speed memories utilizing a fast enable circuit, the delay times of these
decoders and the enable time of the memory are usually less than the typical access time of
the memory. This means that the effective system delay introduced by the decoders is
negligible.
The conditions at the binary-select inputs at the three enable inputs select one of eight output
lines. Two active-low and one active-high enable inputs reduce the need for external gates or
inverters when expanding. A 24-line decoder can be implemented without external inverters
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PRODUCT SUPPORT: TRAINING
PARAMETER NAME SN54HC138
Voltage Nodes (V) 6, 5, 2
Vcc range (V)
2.0 to 6.0
Input Level
CMOS
Output Level
CMOS
Output
2S
From
3
To
8
FEATURES
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DESCRIPTION
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