參數(shù)資料
型號： SN54ALVTH16374WD
廠商： TEXAS INSTRUMENTS INC
元件分類： 總線收發(fā)器
英文描述： ALVT SERIES, DUAL 8-BIT DRIVER, TRUE OUTPUT, CDFP48
封裝： 0.380 INCH, CERAMIC, DFP-48
文件頁數(shù)： 3/14頁
文件大?。?/td> 280K
代理商： SN54ALVTH16374WD
Product Folder : SN74ALVTH16374 - 2.5-V/3.3-V 16-Bit Edge-Triggered D-Type Flip-Flops With 3-State Outputs
Keyword
Part Number
SN74ALVTH16374, Status: ACTIVE
2.5-V/3.3-V 16-Bit Edge-Triggered D-Type Flip-Flops With 3-State Outputs
Related Products
Development Tools
Reference Designs
Datasheet
2.5-V/3.3-V 16-Bit Edge-Triggered D-Type Flip-Flops With 3-State Outputs (Rev.
F) (sn74alvth16374.pdf, 185 KB)
08 Jan 1999 Download
SN74ALVTH16374
Voltage Nodes (V)
3.3, 2.5
Product Information
Features
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q
State-of-the-Art Advanced BiCMOS Technology (ABT) WidebusTM Design for 2.5-V and 3.3-V
Operation and Low Static Power Dissipation
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Support Mixed-Mode Signal Operation (5-V Input and Output Voltages With 2.3-V to 3.6-V VCC)
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Typical VOLP (Output Ground Bounce) < 0.8 V at VCC = 3.3 V, TA = 25°C
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High Drive (-24/24 mA at 2.5-V and -32/64 mA at 3.3-V VCC)
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Power Off Disables Outputs, Permitting Live Insertion
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High-Impedance State During Power Up and Power Down Prevents Driver Conflict
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Uses Bus Hold on Data Inputs in Place of External Pullup/Pulldown Resistors to Prevent the Bus From
Floating
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Auto3-State Eliminates Bus Current Loading When Output Exceeds VCC + 0.5 V
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Latch-Up Performance Exceeds 250 mA Per JESD 17
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ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine
Model; and Exceeds 1000 V Using Charged-Device Model, Robotic Method
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Flow-Through Architecture Facilitates Printed Circuit Board Layout
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Distributed VCC and GND Pin Configuration Minimizes High-Speed Switching Noise
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Package Options Include Plastic Shrink Small-Outline (DL), Thin Shrink Small-Outline (DGG), Thin
Very Small-Outline (DGV) Packages, and 380-mil Fine-Pitch Ceramic Flat (WD) Package
Widebus is a trademark of Texas Instruments Incorporated.
Description
The 'ALVTH16374 devices are 16-bit edge-triggered D-type flip-flops with 3-state outputs designed for 2.5-
V or 3.3-V VCC operation, but with the capability to provide a TTL interface to a 5-V system environment.
These devices are particularly suitable for implementing buffer registers, I/O ports, bidirectional bus
drivers, and working registers.
These devices can be used as two 8-bit flip-flops or one 16-bit flip-flop. On the positive transition of the
clock (CLK), the flip-flops store the logic levels set up at the data (D) inputs.
A buffered output-enable (OE\) input can be used to place the eight outputs in either a normal logic state
(high or low logic levels) or a high-impedance state. In the high-impedance state, the outputs neither load
nor drive the bus lines significantly. The high-impedance state and the increased drive provide the
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