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參數(shù)資料
| 型號(hào)： | SN54AHC74J |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 鎖存器 |
| 英文描述： | AHC SERIES, DUAL POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, CDIP14 |
| 封裝： | CERAMIC, DIP-14 |
| 文件頁數(shù)： | 1/7頁 |
| 文件大?。?/td> | 105K |
| 代理商： | SN54AHC74J |
SN54AHC74, SN74AHC74
DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS
WITH CLEAR AND PRESET
SCLS255G – DECEMBER 1995 – REVISED JANUARY 20000
1
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
D EPIC (Enhanced-Performance Implanted
CMOS) Process
D Operating Range 2-V to 5.5-V VCC
D Latch-Up Performance Exceeds 250 mA Per
JESD 17
D ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF, R = 0)
D Package Options Include Plastic
Small-Outline (D), Shrink Small-Outline
(DB), Thin Very Small-Outline (DGV), Thin
Shrink Small-Outline (PW), and Ceramic
Flat (W) Packages, Ceramic Chip Carriers
(FK), and Standard Plastic (N) and Ceramic
(J) DIPs
description
The ’AHC74 dual positive-edge-triggered devices
are D-type flip-flops.
A low level at the preset (PRE) or clear (CLR)
inputs sets or resets the outputs, regardless of the
levels of the other inputs. When PRE and CLR are
inactive (high), data at the data (D) input meeting
the setup time requirements is transferred to the
outputs on the positive-going edge of the clock
pulse. Clock triggering occurs at a voltage level
and is not directly related to the rise time of the
clock pulse. Following the hold-time interval, data
at the D input can be changed without affecting the
levels at the outputs.
The SN54AHC74 is characterized for operation
over the full military temperature range of –55
°C
to 125
°C. The SN74AHC74 is characterized for
operation from –40
°C to 85°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright
2000, Texas Instruments Incorporated
1
2
3
4
5
6
7
14
13
12
11
10
9
8
1CLR
1D
1CLK
1PRE
1Q
GND
VCC
2CLR
2D
2CLK
2PRE
2Q
SN54AHC74 ...J OR W PACKAGE
SN74AHC74 . . . D, DB, DGV, N, OR PW PACKAGE
(TOP VIEW)
32 1 20 19
910 11 1213
4
5
6
7
8
18
17
16
15
14
2D
NC
2CLK
NC
2PRE
1CLK
NC
1PRE
NC
1Q
1D
1CLR
NC
2Q
V
2CLR
1Q
GND
NC
SN54AHC74 . . . FK PACKAGE
(TOP VIEW)
CC
NC – No internal connection
EPIC is a trademark of Texas Instruments Incorporated.
On products compliant to MIL-PRF-38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SN54AHC74W | 制造商:TI 制造商全稱:Texas Instruments 功能描述:DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH CLEAR AND PRESET |
| SN54AHC86 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:QUADRUPLE 2-INPUT EXCLUSIVE-OR GATES |
| SN54AHC86_07 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:QUADRUPLE 2-INPUT EXCLUSIVE-OR GATES |
| SN54AHC86_08 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:QUADRUPLE 2-INPUT EXCLUSIVE-OR GATES |
| SN54AHC86FK | 制造商:TI 制造商全稱:Texas Instruments 功能描述:QUADRUPLE 2-INPUT EXCLUSIVE-OR GATES |
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