
SN54AHC138, SN74AHC138
3-LINE TO 8-LINE DECODERS/DEMULTIPLEXERS
SCLS258G – DECEMBER 1995 – REVISED JULY 1998
1
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
D Operating Range 2-V to 5.5-V VCC
D EPIC (Enhanced-Performance Implanted
CMOS) Process
D Designed Specifically for High-Speed
Memory Decoders and Data Transmission
Systems
D Incorporate Three Enable Inputs to Simplify
Cascading and/or Data Reception
D Latch-Up Performance Exceeds 250 mA Per
JESD 17
D ESD Protection Exceeds 2000 V Per
MIL-STD-833, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF, R = 0)
D Package Options Include Plastic
Small-Outline (D), Shrink Small-Outline
(DB), Thin Very Small-Outline (DGV), Thin
Shrink Small-Outline (PW), and Ceramic
Flat (W) Packages, Ceramic Chip
Carriers (FK), and Standard Plastic (N) and
Ceramic (J) DIPs
description
The
’AHC138
decoders/demultiplexers
are
designed for high-performance memory-decoding
or data-routing applications requiring very short
propagation-delay times. In high-performance
memory systems, these decoders can be used to
minimize the effects of system decoding. When
employed with high-speed memories utilizing a
fast enable circuit, the delay times of these
decoders and the enable time of the memory are
usually less than the typical access time of the
memory. This means that the effective system
delay introduced by the decoders is negligible.
The conditions at the binary-select inputs and the three enable inputs select one of eight output lines. Two
active-low and one active-high enable inputs reduce the need for external gates or inverters when expanding.
A 24-line decoder can be implemented without external inverters and a 32-line decoder requires only one
inverter. An enable input can be used as a data input for demultiplexing applications.
The SN54AHC138 is characterized for operation over the full military temperature range of –55
°C to 125°C.
The SN74AHC138 is characterized for operation from –40
°C to 85°C.
On products compliant to MIL-PRF-38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
Copyright
1998, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC is a trademark of Texas Instruments Incorporated.
32 1 20 19
910 11 1213
4
5
6
7
8
18
17
16
15
14
Y1
Y2
NC
Y3
Y4
C
G2A
NC
G2B
G1
B
A
NC
Y6
Y5
V
Y0
Y7
GND
NC
SN54AHC138 . . . FK PACKAGE
(TOP VIEW)
CC
NC – No internal connection
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
A
B
C
G2A
G2B
G1
Y7
GND
VCC
Y0
Y1
Y2
Y3
Y4
Y5
Y6
SN54AHC138 ...J OR W PACKAGE
SN74AHC138 . . . D, DB, DGV, N, OR PW PACKAGE
(TOP VIEW)