參數(shù)資料
型號: SN54AC74FK
廠商: TEXAS INSTRUMENTS INC
元件分類: 鎖存器
英文描述: AC SERIES, DUAL POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, CQCC20
封裝: CERAMIC, LCC-20
文件頁數(shù): 9/10頁
文件大?。?/td> 194K
代理商: SN54AC74FK
Product Folder: SN74AC74, Dual Positive-Edge-Triggered D-Type Flip-Flops With Clear and Preset
PRODUCT SUPPORT: TRAINING
SN74AC74, Dual Positive-Edge-Triggered D-Type Flip-Flops With Clear and Preset
DEVICE STATUS: ACTIVE
PARAMETER NAME SN54AC74 SN74AC74
Voltage Nodes (V) 5, 3.3
5, 3.3
Vcc range (V)
2.0 to 6.0 2.0 to 6.0
Input Level
CMOS
Output Level
CMOS
Output Drive (mA)
-24/24
Output
3S
No. of Bits
2
Static Current
0.02
th (ns)
0.5
tpd max (ns)
10.5
tsu (ns)
3
FEATURES
q
2-V to 6-V VCC Operation
q
Inputs Accept Voltages to 6 V
q
Max tpd of 10 ns at 5 V
DESCRIPTION
The ’AC74 devices are dual positive-edge-triggered D-type flip-flops.
A low level at the preset (PRE)\ or clear (CLR)\ input sets or resets the outputs, regardless of the levels of the other inputs. When PRE\ and CLR\ are inactive (high), data at the data (D) input
meeting the setup-time requirements is transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time
of the clock pulse. Following the hold-time interval, data at D can be changed without affecting the levels at the outputs.
TECHNICAL DOCUMENTS
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DATASHEET
Full datasheet in Acrobat PDF: sn74ac74.pdf (103 KB,Rev.D) (Updated: 09/19/2002)
APPLICATION NOTES
View Application Notes for Digital Logic
file:///H|/imaging/BITTING/cpl/20020930_1/09272002_10/TXII/09272002_HTML/sn74ac74.html (1 of 3) [Oct-03-2002 2:43:46 PM]
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