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參數(shù)資料
| 型號： | SN54ABT853FK |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 總線收發(fā)器 |
| 英文描述： | ABT SERIES, 8-BIT TRANSCEIVER, TRUE OUTPUT, CQCC28 |
| 封裝： | CERAMIC, LCC-28 |
| 文件頁數(shù)： | 2/12頁 |
| 文件大?。?/td> | 226K |
| 代理商： | SN54ABT853FK |
Product Folder: SN54ABT853, 8-Bit To 9-Bit Parity Bus Transceivers
Keyword
Part Number
PRODUCT SUPPORT: TRAINING
SN54ABT853, 8-Bit To 9-Bit Parity Bus Transceivers
DEVICE STATUS: ACTIVE
PARAMETER NAME SN54ABT853 SN74ABT853
Voltage Nodes (V) 5
5
Vcc range (V)
4.5 to 5.5
Input Level
TTL
Output Level
TTL
Output Drive (mA)
-32/64
No. of Outputs
8
Logic
True
Static Current
19.12
tpd max (ns)
5.3
FEATURES
q
State-of-the-Art EPIC-II BTM BiCMOS Design Significantly Reduces Power Dissipation
q
ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0)
q
Latch-Up Performance Exceeds 500 mA Per JESD 17
q
Typical VOLP (Output Ground Bounce) < 1 V at VCC = 5 V, TA = 25°C
q
High-Drive Outputs (-32-mA IOH, 64-mA IOL)
q
High-Impedance State During Power Up and Power Down
q
Parity-Error Flag With Parity Generator/Checker
q
Latch for Storage of Parity-Error Flag
q
Package Options Include Plastic Small-Outline (DW), Shrink Small-Outline (DB), and Thin Shrink Small-Outline (PW) Packages, Ceramic Chip Carriers (FK), Ceramic Flat (W) Package, and Plastic (NT)
and Ceramic (JT) DIPs
EPIC-IIB is a trademark of Texas Instruments Incorporated.
DESCRIPTION
The 'ABT853 8-bit to 9-bit parity transceivers are designed for communication between data buses. When data is transmitted from the A bus to the B bus, a parity bit is generated. When data is transmitted
from the B bus to the A bus with its corresponding parity bit, the open-collector parity-error (ERR\) output indicates whether or not an error in the B data has occurred. The output-enable (OEA\ and OEB\)
inputs can be used to disable the device so that the buses are effectively isolated. The 'ABT853 transceivers provide true data at their outputs.
A 9-bit parity generator/checker generates a parity-odd (PARITY) output and monitors the parity of the I/O ports with the ERR\ flag. The parity-error output can be passed, sampled, stored, or cleared from
the latch using the latch-enable (LE\) and clear (CLR\) control inputs. When both OEA\ and OEB\ are low, data is transferred from the A bus to the B bus and inverted parity is generated. Inverted parity is a
forced error condition that gives the designer more system diagnostic capability.
When VCC is between 0 and 2.1 V, the device is in the high-impedance state during power up or power down. However, to ensure the high-impedance state above 2.1 V, OE\ should be tied to VCC through a
pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
TECHNICAL DOCUMENTS
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| SN54ABT853JT | 制造商:TI 制造商全稱:Texas Instruments 功能描述:8-BIT TO 9-BIT PARITY BUS TRANSCEIVERS |
| SN54ABT853W | 制造商:TI 制造商全稱:Texas Instruments 功能描述:8-BIT TO 9-BIT PARITY BUS TRANSCEIVERS |
| SN54ABT8543 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:SCAN TEST DEVICES WITH OCTAL REGISTERED BUS TRANSCEIVERS |
| SN54ABT8543FK | 制造商:TI 制造商全稱:Texas Instruments 功能描述:SCAN TEST DEVICES WITH OCTAL REGISTERED BUS TRANSCEIVERS |
| SN54ABT8543JT | 制造商:TI 制造商全稱:Texas Instruments 功能描述:SCAN TEST DEVICES WITH OCTAL REGISTERED BUS TRANSCEIVERS |
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