- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄374847 > SN54ABT833 (Texas Instruments, Inc.) 8-BIT TO 9-BIT PARITY BUS TRANSCEIVERS PDF資料下載
參數(shù)資料
| 型號： | SN54ABT833 |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | 8-BIT TO 9-BIT PARITY BUS TRANSCEIVERS |
| 中文描述： | 8位至9位奇偶總線收發(fā)器 |
| 文件頁數(shù)： | 1/9頁 |
| 文件大小： | 154K |
| 代理商： | SN54ABT833 |
SN54ABT833, SN74ABT833
8-BIT TO 9-BIT PARITY BUS TRANSCEIVERS
SCBS195C – FEBRUARY 1991 – REVISED JANUARY 1997
1
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
State-of-the-Art EPIC-
ΙΙ
B
BiCMOS Design
Significantly Reduces Power Dissipation
ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF, R = 0)
Latch-Up Performance Exceeds 500 mA Per
JEDEC Standard JESD-17
Typical V
OLP
(Output Ground Bounce) < 1 V
at V
CC
= 5 V, T
A
= 25
°
C
High-Drive Outputs (–32-mA I
OH
,
64-mA I
OL
)
Parity Error Flag With Parity
Generator/Checker
Register for Storage of the Parity Error Flag
Package Options Include Plastic
Small-Outline (DW) Packages, Ceramic
Chip Carriers (FK), and Plastic (NT) and
Ceramic (JT) DIPs
description
The ’ABT833 8-bit to 9-bit parity transceivers are
designed for communication between data buses.
When data is transmitted from the A bus to the
B bus, a parity bit is generated. When data is
transmitted from the B bus to the A bus with its
corresponding parity bit, the open-collector
parity-error (ERR) output indicates whether or not
an error in the B data has occurred. The
output-enable (OEA and OEB) inputs can be used
to disable the device so that the buses are
effectively isolated. The ’ABT833 provide true
data at their outputs.
A 9-bit parity generator/checker generates a
parity-odd (PARITY) output and monitors the
parity of the I/O ports with the ERR flag. ERR is
clocked into the register on the rising edge of the
clock (CLK) input. The error flag register is cleared
with a low pulse on the clear (CLR) input. When
both OEA and OEB are low, data is transferred
from the A bus to the B bus and inverted parity is
generated. Inverted parity is a forced error
condition that gives the designer more system
diagnostic capability.
Copyright
1997, Texas Instruments Incorporated
UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC-
ΙΙ
B is a trademark of Texas Instruments Incorporated.
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
OEA
A1
A2
A3
A4
A5
A6
A7
A8
ERR
CLR
GND
V
CC
B1
B2
B3
B4
B5
B6
B7
B8
PARITY
OEB
CLK
SN54ABT833 . . . JT PACKAGE
SN74ABT833 . . . DW OR NT PACKAGE
(TOP VIEW)
3 2 1 28 27
12 13
5
6
7
8
9
10
11
25
24
23
22
21
20
19
B3
B4
B5
NC
B6
B7
B8
A3
A4
A5
NC
A6
A7
A8
4
26
14 15 16 1718
E
C
G
N
C
O
P
A
A
O
N
B
B
SN54ABT833 . . . FK PACKAGE
(TOP VIEW)
V
C
NC – No internal connection
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| SN54ABT833FK | 8-BIT TO 9-BIT PARITY BUS TRANSCEIVERS |
| SN54ABT833JT | 8-BIT TO 9-BIT PARITY BUS TRANSCEIVERS |
| SN54ABT841FK | 10-BIT BUS-INTERFACE D-TYPE LATCHES WITH 3-STATE OUTPUTS |
| SN54ABT841JT | 10-BIT BUS-INTERFACE D-TYPE LATCHES WITH 3-STATE OUTPUTS |
| SN54ABT841W | 10-BIT BUS-INTERFACE D-TYPE LATCHES WITH 3-STATE OUTPUTS |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SN54ABT833FK | 制造商:TI 制造商全稱:Texas Instruments 功能描述:8-BIT TO 9-BIT PARITY BUS TRANSCEIVERS |
| SN54ABT833JT | 制造商:TI 制造商全稱:Texas Instruments 功能描述:8-BIT TO 9-BIT PARITY BUS TRANSCEIVERS |
| SN54ABT841 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:10-BIT BUS-INTERFACE D-TYPE LATCHES WITH 3-STATE OUTPUTS |
| SN54ABT841FK | 制造商:TI 制造商全稱:Texas Instruments 功能描述:10-BIT BUS-INTERFACE D-TYPE LATCHES WITH 3-STATE OUTPUTS |
| SN54ABT841JT | 制造商:TI 制造商全稱:Texas Instruments 功能描述:10-BIT BUS-INTERFACE D-TYPE LATCHES WITH 3-STATE OUTPUTS |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。