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參數(shù)資料
| 型號： | SMS48GR03 |
| 廠商： | Summit Microelectronics, Inc. |
| 英文描述： | Quad Programmable Precision Supervisory Controller With Independent Resets |
| 中文描述： | 四可編程精密監(jiān)控控制器，獨立重置 |
| 文件頁數(shù)： | 7/16頁 |
| 文件大?。?/td> | 848K |
| 代理商： | SMS48GR03 |
7
2088 1.1 04/11/05
SMS48
SUMMIT MICROELECTRONICS, Inc.
Preliminary Information
SCL (10)
SCL is the serial clock input. It should be tied to V
DD_CAP
through a pull-up resistor.
Figure 4 - Watchdog and WLDI Timing
tPRTO
2047 Fig04 3.0
RESET#
WLDI
t0
t0
t0
t0
t0
tPRTO
tPWDTO
tPWDTO
Figure 5 - V
0-1
Inputs and Resulting RESET# Behavior with V
0
set to UV and V
1
set to OV sensing.
V
0
V
P T H -U V
R E S E T #0
t
D R S T
V
1
V
PT H -O V
R E S E T #1
t
P R TO
t
D R S T
t
P R TO
PIN DESCRIPTIONS (CONTINUED)
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