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參數(shù)資料
| 型號： | SMS48GCR04 |
| 廠商： | Summit Microelectronics, Inc. |
| 英文描述： | Quad Programmable Precision Supervisory Controller With Independent Resets |
| 中文描述： | 四可編程精密監(jiān)控控制器，獨立重置 |
| 文件頁數(shù)： | 15/16頁 |
| 文件大?。?/td> | 848K |
| 代理商： | SMS48GCR04 |
15
2088 1.1 04/11/05
SMS48
SUMMIT MICROELECTRONICS, Inc.
Preliminary Information
PACKAGE
16 PIN SSOP PACKAGE
0.007 - 0.010
(0.18 - 0.25)
0.150 - 0.157
(3.81 - 3.99)
0.025
(0.635)
0.016 - 0.050
(0.41 - 1.27)
0.008 - 0.012
(0.20 - 0.31)
0.189 - 0.197
(4.80 - 5.00)
0.228 - 0.244
(5.79 - 6.20)
Pin 1
0.004 - 0.010
(0.10 - 0.25)
0.059
(1.50)
0.053 - 0.069
(1.35 - 1.75)
MAX
16 Pin SSOP
Ref. JEDEC MO-137
Inches
(Millimeters)
0” Min to
8” Max
DEFAULT CONFIGURATION REGISTER SETTINGS - SMS48GC-370
The default device ordering number is SMS48GC-370, is programmed as described above and tested
over the commercial temperature range.
Register
Contents
Function
R00
56
V0 threshold set to 3.090V
R01
28
V1 threshold set to 2.400V
R02
A0
V2 threshold set to 1.400V
R03
14
V3 threshold set to 0.700V
R04
F3
Reset Trigger source set for all channels, V0, V1 set to high range and V2, V3
set to low range
R05
X0
Upper bits are volatile status indication of input supply condition. V0, V1, V2
and V3 set to monitor UV Under Voltage.
R06
C5
Reset timeout set to 100ms, W atchdog Timer set to 1.6s. Bits D4 and D3
indicate revision control.
R07
40
Configuration registers are unlocked.
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相關(guān)代理商/技術(shù)參數(shù) |
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| SMS48GCR05 | 制造商:SUMMIT 制造商全稱:SUMMIT 功能描述:Quad Programmable Precision Supervisory Controller With Independent Resets |
| SMS48GCR06 | 制造商:SUMMIT 制造商全稱:SUMMIT 功能描述:Quad Programmable Precision Supervisory Controller With Independent Resets |
| SMS48GCR07 | 制造商:SUMMIT 制造商全稱:SUMMIT 功能描述:Quad Programmable Precision Supervisory Controller With Independent Resets |
| SMS48GR00 | 制造商:SUMMIT 制造商全稱:SUMMIT 功能描述:Quad Programmable Precision Supervisory Controller With Independent Resets |
| SMS48GR01 | 制造商:SUMMIT 制造商全稱:SUMMIT 功能描述:Quad Programmable Precision Supervisory Controller With Independent Resets |
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