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參數(shù)資料
| 型號： | SMS47GR02 |
| 廠商： | Summit Microelectronics, Inc. |
| 英文描述： | Quad Programmable Precision Cascade Sequencer and Supervisory Controller |
| 中文描述： | 四可編程精密級聯(lián)序列和監(jiān)督控制器 |
| 文件頁數(shù)： | 13/19頁 |
| 文件大?。?/td> | 923K |
| 代理商： | SMS47GR02 |
13
2087 1.0 04/11/05
SMS47
SUMMIT MICROELECTRONICS, Inc.
Preliminary Information
Table 10. I
2
C Operating Characteristics
Figure 9. I
2
C Operating Characteristics
I
2
C PROGRAMMING INFORMATION
Note (1): These values are guaranteed by design.
CONFIGURATION REGISTER OPERATION
Data for the configuration registers is read and written via
the I
2
C industry standard two-wire interface. The bus was
designed for two-way, two-line serial communication be-
tween different integrated circuits. The two lines are a
serial data line (SDA) and a serial clock line (SCL). The
SDA line must be connected to a positive supply by a pull-
up resistor, located somewhere on the bus. See Operating
Characteristics: Table 10 and Figure 9 below.
Input Data Protocol
The protocol defines any device that sends data onto the
bus as a transmitter and any device that receives data as
a receiver. The device controlling data transmission is
called the Master and the controlled device is called the
Slave. In all cases the SMS47 will be a Slave device, since
it never initiates any data transfers.
One data bit is transferred during each clock pulse. The
data on the SDA line must remain stable during clock high
time because changes on the data line while SCL is high
will be interpreted as start or stop condition.
tF
tR
tLOW
tHIGH
tHD:STA
tSU:STA
tBUF
tDH
tHD:DAT
tSU:DAT
tSU:STO
SCL
SDA In
SDA Out
tAA
2047 Fig09
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