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參數(shù)資料
| 型號(hào)： | SMS46GR04 |
| 廠商： | Summit Microelectronics, Inc. |
| 英文描述： | Quad Programmable Precision Supervisory Controller With Independent Resets and 4k-Bit Nonvolatile Memory |
| 中文描述： | 四可編程精密監(jiān)控控制器，獨(dú)立重置和4K位的非易失性內(nèi)存 |
| 文件頁(yè)數(shù)： | 13/17頁(yè) |
| 文件大?。?/td> | 918K |
| 代理商： | SMS46GR04 |
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13
2083 1.1 06/04/04
SMS46
SUMMIT MICROELECTRONICS, Inc.
Preliminary Information
Figure 9 - Read and Write Operations
The high order bits of the address byte remain constant.
Should the Master transmit more than 16 bytes, prior to
generating the Stop condition, the address counter will
rollover and the previously written data will be overwrit-
ten. As with the byte Write operation, all inputs are disabled
during the internal Write cycle. Refer to Figure 11 for the
address, Acknowledge, and data transfer sequence.
N
A
C
K
N
A
C
K
Typical Write Operation
(Standard memory device type)
S
T
A
R
T
A
C
K
B
A
2
B
A
1
A
8
R
/
W
A
C
K
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
A
C
K
S
T
O
P
Master
SDA
Slave
0
1
1 0
A
C
R
/
W
A
C
K
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
A
C
K
S
T
O
P
S
T
A
R
T
Writing Configuration Registers
Master
SDA
Slave
0 1
1 0
Master
SDA
Slave
Device Type
Address
Bus
Address
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
C
7
C
6
C
5
C
4
C
3
C
2
C
1
C
0
A
C
K
R
/
W
A
C
K
S
T
A
R
T
C
7
C
6
C
C
4
C
3
C
2
C
1
C
0
Reading the Configuration Register
0 1
1 0
A
C
K
R
/
W
S
T
O
P
S
T
A
R
T
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
0 1
1 0
Up to 15
additional bytes
can be written
before issuing
the stop.
B
A
2
B
A
1
X
B
A
2
B
A
1
X
B
A
2
B
A
1
X
2047 Fig11
Typical Reading Operation
(Alternate memory device type)
Master
SDA
Slave
A
C
K
R
/
W
A
C
K
S
T
A
R
T
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
1 1
1 0
A
C
K
R
/
W
S
T
O
P
S
T
A
R
T
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
1 1
1 0
B
A
2
B
A
1
A
8
B
A
2
B
A
1
A
8
I
2
C INTERFACE (CONTINUED)
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