參數(shù)資料
型號(hào)： SMS45GCR07
廠商： Summit Microelectronics, Inc.
英文描述： Quad Programmable Precision Cascade Sequencer and Supervisory Controller with 4k-Bit Nonvolatile Memory
中文描述： 四可編程精密級(jí)聯(lián)序列和監(jiān)督控制器4K的位的非易失性內(nèi)存
文件頁(yè)數(shù)： 16/20頁(yè)
文件大?。?/td> 993K
代理商： SMS45GCR07
16
SMS45
2079 1.2 05/24/04
SUMMIT MICROELECTRONICS, Inc.
Preliminary Information
Figure 12. Write Flow Chart
Acknowledge Polling
When the SMS45 is performing an internal Write operation
it will ignore any new Start conditions. Since the device will
only return an acknowledge after it accepts the Start the
part can be continuously queried until an acknowledge is
issued, indicating that the internal Write cycle is complete.
See the flow chart for the proper sequence of operations for
polling.
READ OPERATIONS
Read operations are initiated with the R/W bit of the
identification field set to 1. There are two different Read
options: 1. Current Address Byte Read, and 2. Random
Address Byte Read.
Current Address Read (memory only)
The SMS45 contains an internal address counter which
maintains the address of the last word accessed, incre-
mented by one. If the last address accessed (either a
Read or Write) was to address location n, the next Read
operation would access data from address location n+1
and increment the current address pointer. When the
SMS45 receives the Slave address field with the R/W bit
set to 1 it issues an acknowledge and transmits the 8-Bit
word stored at address location n+1. The current address
byte Read operation only accesses a single byte of data.
The Master sets the SDA line to NACK and generates a
stop condition. At this point the SMS45 discontinues data
transmission.
Random Address Read (Register and Memory)
Random address Read operations allow the Master to
access any memory location in a random fashion. This
operation involves a two-step process. First, the Master
issues a write command which includes the start condi-
tion and the Slave address field (with the R/W bit set to
Write), followed by the address of the word it is to Read.
This procedure sets the internal address counter of the
SMS45 to the desired address. After the word address
acknowledge is received by the Master it immediately
reissues a Start condition, followed by another Slave
address field with the R/W bit set to READ. The SMS45 will
respond with an Acknowledge and then transmit the 8 data
bits stored at the addressed location. At this point the
Master sets the SDA line to NACK and generates a Stop
condition. The SMS45 discontinues data transmission and
reverts to its standby power mode.
Sequential READ (Memory Only)
Sequential Reads can be initiated as either a current
address Read or random access Read. The first word is
transmitted as with the other byte Read modes (current
address byte Read or random address byte Read);
however, the Master now responds with an Acknowledge,
indicating that it requires additional data from the SMS45.
The SMS45 continues to output data for each Acknowl-
edge received. The Master terminates the sequential
Read operation by responding with a NACK, and issues
a Stop condition. During a sequential Read operation the
internal address counter is automatically incremented
with each Acknowledge signal. For Read operations all
address bits are incremented, allowing the entire array to
be read using a single Read command. After a count of
the last memory address the address counter will rollover
and the memory will continue to output data.
Next
Operation
a Write
ACK
Returned
Issue
Address
Proceed
With
Write
Await
Next
Command
Issue Stop
Issue Slave
Address and
R/W = 0
Issue Stop
Write Cycle
In Progress
Yes
No
Issue Start
2047 Fig12
Yes
No
I
2
C PROGRAMMING INFORMATION (CONTINUED)
相關(guān)PDF資料
PDF描述
SMS45GR00 Quad Programmable Precision Cascade Sequencer and Supervisory Controller with 4k-Bit Nonvolatile Memory
SMS45GR01 Quad Programmable Precision Cascade Sequencer and Supervisory Controller with 4k-Bit Nonvolatile Memory
SMS45GR02 Quad Programmable Precision Cascade Sequencer and Supervisory Controller with 4k-Bit Nonvolatile Memory
SMS45GR03 Quad Programmable Precision Cascade Sequencer and Supervisory Controller with 4k-Bit Nonvolatile Memory
SMS45GR04 Quad Programmable Precision Cascade Sequencer and Supervisory Controller with 4k-Bit Nonvolatile Memory
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
SMS45GR00 制造商:SUMMIT 制造商全稱:SUMMIT 功能描述:Quad Programmable Precision Cascade Sequencer and Supervisory Controller with 4k-Bit Nonvolatile Memory
SMS45GR01 制造商:SUMMIT 制造商全稱:SUMMIT 功能描述:Quad Programmable Precision Cascade Sequencer and Supervisory Controller with 4k-Bit Nonvolatile Memory
SMS45GR02 制造商:SUMMIT 制造商全稱:SUMMIT 功能描述:Quad Programmable Precision Cascade Sequencer and Supervisory Controller with 4k-Bit Nonvolatile Memory
SMS45GR03 制造商:SUMMIT 制造商全稱:SUMMIT 功能描述:Quad Programmable Precision Cascade Sequencer and Supervisory Controller with 4k-Bit Nonvolatile Memory
SMS45GR04 制造商:SUMMIT 制造商全稱:SUMMIT 功能描述:Quad Programmable Precision Cascade Sequencer and Supervisory Controller with 4k-Bit Nonvolatile Memory
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