參數(shù)資料
型號(hào)： SMS45GCR00
廠商： Summit Microelectronics, Inc.
英文描述： Quad Programmable Precision Cascade Sequencer and Supervisory Controller with 4k-Bit Nonvolatile Memory
中文描述： 四可編程精密級(jí)聯(lián)序列和監(jiān)督控制器4K的位的非易失性內(nèi)存
文件頁數(shù)： 13/20頁
文件大?。?/td> 993K
代理商： SMS45GCR00
13
2079 1.2 05/24/04
SMS45
SUMMIT MICROELECTRONICS, Inc.
Preliminary Information
Table 10. I
2
C Operating Characteristics
2047 Table10 4.0
Figure 9. I
2
C Operating Characteristics
I
2
C PROGRAMMING INFORMATION
Note (1): These values are guaranteed by design.
MEMORY OPERATION
Data for the configuration registers and the memory array
are read and written via an industry standard two-wire
interface. The bus was designed for two-way, two-line
serial communication between different integrated cir-
cuits. The two lines are a serial data line (SDA) and a
serial clock line (SCL). The SDA line must be connected
to a positive supply by a pull-up resistor, located some-
where on the bus. See Memory Operating Characteris-
tics: Table 10 and Figure 9.
Input Data Protocol
The protocol defines any device that sends data onto the
bus as a transmitter and any device that receives data as
a receiver. The device controlling data transmission is
called the Master and the controlled device is called the
Slave. In all cases the SMS45 will be a Slave device, since
it never initiates any data transfers.
One data bit is transferred during each clock pulse. The
data on the SDA line must remain stable during clock high
time because changes on the data line while SCL is high
will be interpreted as start or stop condition.
tF
tR
tLOW
tHIGH
tHD:STA
tSU:STA
tBUF
tDH
tHD:DAT
tSU:DAT
tSU:STO
SCL
SDA In
SDA Out
tAA
2047 Fig09
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相關(guān)PDF資料
PDF描述
SMS45GCR01 Quad Programmable Precision Cascade Sequencer and Supervisory Controller with 4k-Bit Nonvolatile Memory
SMS45GCR02 Quad Programmable Precision Cascade Sequencer and Supervisory Controller with 4k-Bit Nonvolatile Memory
SMS45GCR03 Quad Programmable Precision Cascade Sequencer and Supervisory Controller with 4k-Bit Nonvolatile Memory
SMS45GCR04 Quad Programmable Precision Cascade Sequencer and Supervisory Controller with 4k-Bit Nonvolatile Memory
SMS45GCR05 Quad Programmable Precision Cascade Sequencer and Supervisory Controller with 4k-Bit Nonvolatile Memory
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
SMS45GCR01 制造商:SUMMIT 制造商全稱:SUMMIT 功能描述:Quad Programmable Precision Cascade Sequencer and Supervisory Controller with 4k-Bit Nonvolatile Memory
SMS45GCR02 制造商:SUMMIT 制造商全稱:SUMMIT 功能描述:Quad Programmable Precision Cascade Sequencer and Supervisory Controller with 4k-Bit Nonvolatile Memory
SMS45GCR03 制造商:SUMMIT 制造商全稱:SUMMIT 功能描述:Quad Programmable Precision Cascade Sequencer and Supervisory Controller with 4k-Bit Nonvolatile Memory
SMS45GCR04 制造商:SUMMIT 制造商全稱:SUMMIT 功能描述:Quad Programmable Precision Cascade Sequencer and Supervisory Controller with 4k-Bit Nonvolatile Memory
SMS45GCR05 制造商:SUMMIT 制造商全稱:SUMMIT 功能描述:Quad Programmable Precision Cascade Sequencer and Supervisory Controller with 4k-Bit Nonvolatile Memory
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