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參數資料
| 型號： | SMS2904S2.7 |
| 廠商： | Summit Microelectronics, Inc. |
| 英文描述： | Voltage Supervisory Circuit With Watchdog Timer |
| 中文描述： | 電壓監(jiān)控電路，帶有看門狗定時器 |
| 文件頁數： | 9/14頁 |
| 文件大?。?/td> | 161K |
| 代理商： | SMS2904S2.7 |
SMS2902/SMS2904/SMS2916
9
2028 5.1 8/2/00
FIGURE 9. CURRENT ADDRESS BYTE READ MODE
FIGURE 8. ACKNOWLEDGE POLLING
Acknowledge Polling
When the SMS29xx is performing an internal WRITE
operation, it will ignore any new START conditions. Since
the device will only return an acknowledge after it accepts
the START, the part can be continuously queried until an
acknowledge is issued, indicating that the internal WRITE
cycle is complete.
To poll the device, give it a START condition, followed by
a slave address for a WRITE operation (See Figure 8).
READ OPERATIONS
Read operations are initiated with the R/W bit of the
identification field set to
“
1.
”
There are four different read
options:
1.
2.
3.
4.
Current Address Byte Read
Random Address Byte Read
Current Address Sequential Read
Random Address Sequential Read
Current Address Byte Read
The SMS29xx contains an internal address counter which
maintains the address of the last word accessed,
incremented by one. If the last address accessed (either
a read or write) was to address location n, the next read
operation would access data from address location n+1
and increment the current address pointer. When the
SMS29xx receives the slave address field with the R/W bit
set to
“
1,
”
it issues an acknowledge and transmits the 8-
bit word stored at address location n+1.
The current address byte read operation only accesses a
single byte of data. The master does not acknowledge the
transfer, but does generate a stop condition. At this point,
the SMS29xx discontinues data transmission. See Figure
9 for the address acknowledge and data transfer se-
quence.
Issue Start
Internal WRITE Cycle
In Progress;
Begin ACK Polling
Issue Slave
Address and
R/W = 0
ACK
Returned
Next
operation a
WRITE
Issue Byte
Address
Proceed with
WRITE
Issue Stop
Await Next
Command
Issue Stop
No
No
Yes (Internal WRITE Cycle is completed)
Yes
2028 ILL10.0
S
T
A
R
T
S
T
O
P
Slave Address
Device
Type
Address
Read/Write
1= Read
SDA Bus Activity
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
Master sends Read
request to Slave
Slave sends
Data to Master
Slave Transmitter
to
Master Receiver
Master Transmitter
to
Slave Receiver
1
1
1
0
0
1
Lack of ACK (low)
from Master
determines last
data byte to be read
1
Shading Denotes
SMS29xx
SDA Output Active
X
X
R
W
A
C
K
X
Data Byte
2028 ILL11.1
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PDF描述 |
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| SMS2904SA | Voltage Supervisory Circuit With Watchdog Timer |
| SMS2904SB | Voltage Supervisory Circuit With Watchdog Timer |
| SMS2916S | Voltage Supervisory Circuit With Watchdog Timer |
| SMS2916S2.7 | Voltage Supervisory Circuit With Watchdog Timer |
| SMS2916SA | Voltage Supervisory Circuit With Watchdog Timer |
相關代理商/技術參數 |
參數描述 |
|---|---|
| SMS2904SA | 制造商:SUMMIT 制造商全稱:SUMMIT 功能描述:Voltage Supervisory Circuit With Watchdog Timer |
| SMS2904SB | 制造商:SUMMIT 制造商全稱:SUMMIT 功能描述:Voltage Supervisory Circuit With Watchdog Timer |
| SMS2916 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Precision Voltage Supervisory Circuit With Watchdog Timer and 16K I2C Memory |
| SMS2916P2.7 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Precision Voltage Supervisory Circuit With Watchdog Timer and 16K I2C Memory |
| SMS2916P2.7T | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Precision Voltage Supervisory Circuit With Watchdog Timer and 16K I2C Memory |
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