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參數(shù)資料
| 型號： | SMS2902S2.7 |
| 廠商： | Summit Microelectronics, Inc. |
| 英文描述： | Voltage Supervisory Circuit With Watchdog Timer |
| 中文描述： | 電壓監(jiān)控電路，帶有看門狗定時器 |
| 文件頁數(shù)： | 11/14頁 |
| 文件大?。?/td> | 161K |
| 代理商： | SMS2902S2.7 |
SMS2902/SMS2904/SMS2916
11
2028 5.1 8/2/00
Sequential READ
Sequential READs can be initiated as either a current
address READ or random access READ. The first word is
transmitted as with the other byte read modes (current
address byte READ or random address byte READ);
however, the master now responds with an ACKnowledge,
indicating that it requires additional data from the
SMS29xx. The SMS29xx continues to output data for
each ACKnowledge received. The master terminates the
sequential READ operation by not responding with an
ACKnowledge, and issues a STOP conditions.
During a sequential read operation, the internal address
counter is automatically incremented with each acknowl-
edge signal. For read operations, all address bits are
incremented, allowing the entire array to be read using a
single read command. After a count of the last memory
address, the address counter will
‘
roll-over
’
and the
memory will continue to output data. See Figure 11 for the
address, acknowledge and data transfer sequence.
FIGURE 11. SEQUENTIAL READ OPERATION (starting with a Random Address READ)
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
Shading Denotes
SMS29xx
SDA Output Active
S
T
A
R
T
Word Address
S
T
O
P
A
C
K
Acknowledges from SMS29xx
Slave Address
Slave Address
Device
Type
Address
Read/Write
0= Write
Device
Type
Address
SDA Bus
Activity
S
T
A
R
T
Read/Write
1= Read
X
R
W
X
Acknowledge from
Master Receiver
A
C
K
A
C
K
A
C
K
Master sends Read
request to Slave
Master Writes Word
Address to Slave
Master Requests
Data from Slave
Slave sends
Data to Master
Slave Transmitter
to
Master Receiver
Slave Transmitter
to
Master Receiver
Master Transmitter
to
Slave Receiver
1 0 1 0
1 0 1 0
1
0
Slave sends
Data to Master
X
X
R
W
A
10
A
9
A
10
A
9
X
Lack of ACK (low)
determines last
data byte to be read
1
Lack of
Acknowledge from
Master Receiver
Slave Transmitter
to
Master Receiver
Master Transmitter
to
Slave Receiver
Master Transmitter
to
Slave Receiver
Master Transmitter
to
Slave Receiver
Slave Transmitter
to
Master Receiver
Slave Transmitter
to
Master Receiver
Last Data Byte
First Data Byte
2028 ILL13.1
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| SMS2902SA | Voltage Supervisory Circuit With Watchdog Timer |
| SMS2902SB | Voltage Supervisory Circuit With Watchdog Timer |
| SMS2904S | Voltage Supervisory Circuit With Watchdog Timer |
| SMS2904S2.7 | Voltage Supervisory Circuit With Watchdog Timer |
| SMS2904SA | Voltage Supervisory Circuit With Watchdog Timer |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SMS2902SA | 制造商:SUMMIT 制造商全稱:SUMMIT 功能描述:Voltage Supervisory Circuit With Watchdog Timer |
| SMS2902SB | 制造商:SUMMIT 制造商全稱:SUMMIT 功能描述:Voltage Supervisory Circuit With Watchdog Timer |
| SMS2904S | 制造商:SUMMIT 制造商全稱:SUMMIT 功能描述:Voltage Supervisory Circuit With Watchdog Timer |
| SMS2904S2.7 | 制造商:SUMMIT 制造商全稱:SUMMIT 功能描述:Voltage Supervisory Circuit With Watchdog Timer |
| SMS2904SA | 制造商:SUMMIT 制造商全稱:SUMMIT 功能描述:Voltage Supervisory Circuit With Watchdog Timer |
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