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參數(shù)資料
| 型號(hào)： | SMS1242S-A |
| 廠商： | Summit Microelectronics, Inc. |
| 英文描述： | 2.5V, 3V, 3.3V & 5V Dual Voltage, Dual Reset Microprocessor Supervisory Circuits |
| 中文描述： | 為2.5V，3V，3.3V的 |
| 文件頁(yè)數(shù)： | 8/11頁(yè) |
| 文件大?。?/td> | 82K |
| 代理商： | SMS1242S-A |
8
SMS1242
2038 2.0 6/8/00
SUMMIT MICROELECTRONICS, Inc.
Next
Operation
a Write
ACK
Returned
Issue
Address
Proceed
With
Write
Await
Next
Command
Issue Stop
Issue Slave
Address and
R/W = 0
Issue Stop
Write Cycle
In Progress
Yes
No
Issue Start
2038 Flow01 2.0
Yes
No
Should the master transmit more than 16 bytes, prior to
generating the STOP condition, the address counter will
“
roll over
”
and the previously written data will be overwrit-
ten. As with the byte-write operation, all inputs are
disabled during the internal write cycle. Refer to Figure 8
for the address, ACKnowledge and data transfer se-
quence.
Acknowledge Polling
When the SMS1242 is performing an internal WRITE
operation it will ignore any new START conditions. Since
the device will only return an acknowledge after it accepts
the START, the part can be continuously queried until an
acknowledge is issued, indicating that the internal WRITE
cycle is complete. See the flow diagram for the proper
sequence of operations for polling.
READ OPERATIONS
Read operations are initiated with the R/W bit of the
identification field set to
“
1.
”
There are two different read
options:
1. Current Address Byte Read
2. Random Address Byte Read
Current Address Read
The SMS1242 contains an internal address counter which
maintains the address of the last word accessed, incre-
mented by one. If the last address accessed (either a read
Figure 8. Memory Operation
A
C
K
X
X
X
R
/
W
A
C
K
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
A
C
K
D
7
D
6
D
1
D
0
S
T
O
P
S
T
A
R
T
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
S
T
A
R
T
A
C
K
R
/
W
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
A
C
K
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
A
C
K
D
7
D
6
D
1
D
0
A
C
K
S
T
O
P
Typical Write Operation
Typical Read Operation
Master
SDA
Slave
Master
SDA
Slave
2038 T Fig08 2.0
A
1
0
A
9
A
8
MEMORY OPERATION
(Continued)
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PDF描述 |
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| SMS1242S-B | 2.5V, 3V, 3.3V & 5V Dual Voltage, Dual Reset Microprocessor Supervisory Circuits |
| SMS1242S-C | 2.5V, 3V, 3.3V & 5V Dual Voltage, Dual Reset Microprocessor Supervisory Circuits |
| SMS1242S-D | 2.5V, 3V, 3.3V & 5V Dual Voltage, Dual Reset Microprocessor Supervisory Circuits |
| SMS1242S-E | 2.5V, 3V, 3.3V & 5V Dual Voltage, Dual Reset Microprocessor Supervisory Circuits |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SMS1242S-B | 制造商:SUMMIT 制造商全稱:SUMMIT 功能描述:2.5V, 3V, 3.3V & 5V Dual Voltage, Dual Reset Microprocessor Supervisory Circuits |
| SMS1242S-C | 制造商:SUMMIT 制造商全稱:SUMMIT 功能描述:2.5V, 3V, 3.3V & 5V Dual Voltage, Dual Reset Microprocessor Supervisory Circuits |
| SMS1242S-D | 制造商:SUMMIT 制造商全稱:SUMMIT 功能描述:2.5V, 3V, 3.3V & 5V Dual Voltage, Dual Reset Microprocessor Supervisory Circuits |
| SMS1242S-E | 制造商:SUMMIT 制造商全稱:SUMMIT 功能描述:2.5V, 3V, 3.3V & 5V Dual Voltage, Dual Reset Microprocessor Supervisory Circuits |
| SMS1242S-F | 制造商:SUMMIT 制造商全稱:SUMMIT 功能描述:2.5V, 3V, 3.3V & 5V Dual Voltage, Dual Reset Microprocessor Supervisory Circuits |
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