
SMR101
Preliminary Information
Summit Microelectronics, Inc
209
1
2.1 4/21/2005
2
Figure 2 – SMR101 Operation and timing diagram.
The SMR101 is a programmable reset controller that
monitors the power supply in μP and digital systems
for under voltage conditions The integrated feature set
provides excellent circuit reliability and low cost by
eliminating
external
components
programmable settings allow “on the fly” adjustments
necessary for modern control techniques.
The device performs several functions: it first asserts a
“soft” reset signal whenever the VDD supply voltage
declines below a preset threshold, keeping it asserted
for a programmable time period after VDD has risen
above the reset threshold. The part also provides a
push button input with two programmable delays for
hierarchical manual system reset.
The open-drain SOFT_RST# and HARD_RST#
outputs have on-chip 100K pull-up resistors and do not
require external pull-up resistors unless more drive
current is needed (see figure 3). The SOFT_RST#
comparator is designed to ignore fast transients on
VDD, and the output is guaranteed to be in the correct
logic state for VDD down to 1V. Low supply current
makes the SMR101 ideal for use in portable
equipment. The RESET_IN# input includes a
programmable hold-down delay timer for use with a
push button switch for consumer equipment such as
set-top boxes and PCs.
A microprocessor’s (μP’s) reset input starts the μP in a
known state. The SMR101 asserts a SOFT_RST# to
while
the
prevent code execution errors during power-up,
power-down,
or
UnderVoltage
whenever the VDD supply voltage declines below a
programmed limit (V
MON
). There are 8 programmable
voltage settings to trigger the SOFT_RST# output.
SOFT_RST# stays asserted for a programmable
period after VDD has risen above the reset threshold.
The SOFT_RST# signal is also asserted whenever the
RESET_IN# input is asserted for a programmed delay.
There are 8 programmable timing settings (T
RESET_SR
)
to trigger SOFT_RST# output. The HARD_RST#
signal is also asserted whenever the RESET_IN#
input is asserted for a separate programmed delay.
There are 8 programmable timing settings (T
RESET_HR
)
to trigger the HARD_RST# output. It is recommended
that the soft reset time be of a shorter duration than
that of the HARD_RST#.
In addition to issuing a reset to the μP during power-
up, power-down, and brownout conditions, the
SMR101 is immune to short-duration VDD transients
(glitches) due to an internal glitch filter. A external
0.1μF bypass capacitor mounted as close as possible
to the VDD pin provides additional transient immunity.
Since the SOFT_RST# and HARD_RST# outputs are
open drain, the device interfaces easily with μPs that
have
bidirectional-reset
SOFT_RST# output directly to the μP’s RESET pin
allows either the μP or the SMR101 to assert a reset.
.
(UV)
conditions
pins.
Connecting
the
GENERAL DESCRIPTION
VDD
HARD_RST#
SOFT_RST#
RESET_IN#
Push-Button
Input
T
RESET
T
RESET_HR
T
RESET
VMON
T
GLITCH
Push-Button
Released
T
RESET
Push-Button
Engaged
Push-Button
Engaged
Push-Button
Released
T
RESET
T
RESET_SR
T
RESET_SR