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參數(shù)資料
| 型號(hào)： | SMR100E |
| 廠商： | Summit Microelectronics, Inc. |
| 英文描述： | Programmable Long-Delay Push-Button Reset Controller for Consumer Equipment |
| 中文描述： | 可編程長(zhǎng)延遲按鈕復(fù)位控制器的消費(fèi)電子設(shè)備 |
| 文件頁(yè)數(shù)： | 2/9頁(yè) |
| 文件大小： | 603K |
| 代理商： | SMR100E |
SMR100
Preliminary Information
Summit Microelectronics, Inc
2076 1.6 06/30/04
2
GENERAL DESCRIPTION
The SMR100 is a programmable Reset Controller for
Consumer Equipment used to monitor the power
supply in μP and digital systems. It provides excellent
circuit reliability and low cost by eliminating external
components and adjustments when used with +3.3V
powered circuits. The device performs several
functions: it first asserts a ‘bad power’ signal and then
a reset signal whenever the VDD supply voltage
declines below two preset thresholds, keeping it
asserted for a programmable time period after VDD
has risen above the reset threshold. The part also
provides a programmable delay push button input for
manual system reset.
The open-drain RESET_OUT# and BAD_PWR#
outputs have on-chip 100K pull-up resistors and do not
require external pull-up resistors unless more drive
current is needed (see figure 3). The RESET_OUT#
and BAD_PWR# comparators are designed to ignore
fast transients on VDD, and the outputs are
guaranteed to be in the correct logic state for VDD
down to 1V. Low supply current makes the SMR100
ideal for use in portable equipment. The RESET_IN#
input includes a programmable hold-down delay timer
for use with a push button switch for consumer
equipment such as set-top boxes and PCs.
A microprocessor’s (μP’s) reset input starts the μP in a
known state. The SMR100 asserts a reset to prevent
code -execution errors during power-up, power-down,
or UnderVoltage (UV) conditions. It asserts a
RESET_OUT# signal whenever the VDD supply
voltage declines below a 3.0V threshold, keeping it
asserted for a programmable period after VDD has
risen above the reset threshold. It also asserts a Bad
Power signal to warn of an impending reset or
brownout condition to allow time for the system to
save data before a reset occurs. The BAD_PWR#
signal is also asserted whenever RESET_OUT# is
asserted to prevent erroneous or false Bad Power
warnings during initial turn-on.
In addition to issuing a reset to the μP during power-
up, power-down, and brownout conditions, the
SMR100 is immune to short-duration VDD transients
(glitches) due to a programmable glitch filter. Typically,
a VDD transient of 100mV less than the reset
threshold and lasting for a duration less than the
programmed glitch filter setting will not cause a reset
pulse. A 0.1μF bypass capacitor mounted as close as
possible to the VDD pin provides additional transient
immunity. Since the BAD_PWR# and RESET_OUT#
outputs are open drain, the device interfaces easily
with μPs that have bidirectional-reset pins. Connecting
the RESET_OUT# output directly to the μP’s RESET
pin allows either the μP or the SMR100 to assert a
reset.
VDD
RESET_OUT#
BAD_PWR#
RESET_IN#
Push-Button
Input
T
RESET
T
RESET_HD
T
RESET
3.1V
3.0V
T
GLITCH
Push-Button
Released
Figure 2 – SMR100 Operation and timing diagram
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