VOS
參數(shù)資料
型號: SMP04ESZ
廠商: Analog Devices Inc
文件頁數(shù): 10/15頁
文件大?。?/td> 0K
描述: IC AMP SAMPLE HOLD CMOS 16SOIC
標準包裝: 48
放大器類型: 采樣和保持
電路數(shù): 4
轉(zhuǎn)換速率: 4 V/µs
電流 - 輸入偏壓: 500nA
電壓 - 輸入偏移: 2500µV
電流 - 電源: 4mA
電流 - 輸出 / 通道: 1.2mA
電壓 - 電源,單路/雙路(±): 5 V ~ 12 V,±2.5 V ~ 6 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 16-SOIC(0.154",3.90mm 寬)
供應(yīng)商設(shè)備封裝: 16-SOIC
包裝: 管件
產(chǎn)品目錄頁面: 768 (CN2011-ZH PDF)
–4–
SMP04
REV. D
WAFER TEST LIMITS
SMP04G
Parameter
Symbol
Conditions
Limits
Units
Buffer Offset Voltage
VOS
VIN = +6 V
±10
mV max
Hold Step
VHS
VIN = +6 V
±4
mV max
Droop Rate
V/tV
IN = +6 V
25
mV/s max
Output Source Current
ISOURCE
VIN = +6 V
1.2
mA min
Output Sink Current
ISINK
VIN = +6 V
0.5
mA min
Output Voltage Range
OVR
RL = 20 k
0.06/10.0
V min/max
RL = 10 k
0.06/9.5
V min/max
LOGIC CHARACTERISTICS
Logic Input High Voltage
VINH
2.4
V min
Logic Input Low Voltage
VINL
0.8
V max
Logic Input Current
IIN
1
A max
SUPPLY CHARACTERISTICS
Power Supply Rejection Ratio
PSRR
10.8 V
≤ V
DD
≤ 13.2 V
60
dB min
Supply Current
IDD
7
mA max
Power Dissipation
PDIS
84
mW max
NOTE
Electrical tests are performed at wafer probe to the limits shown. Due to variations in assembly methods and normal yield loss, yield after packaging is not guaranteed
for standard product dice. Consult factory to negotiate specifications based on dice lot qualifications through sample lot assembly and testing.
(@ VDD = +12 V, VSS = DGND = 0 V, RL = No Load, TA = +25 C, unless otherwise noted.)
VOUT3
VOUT1
VOUT2
VOUT4
VIN1
VIN2
VIN3
VIN4
S/H1
S/H3
S/H4
DGND
VSS
VDD
S/H2
Dice Characteristics
Die Size: 0.80 x 0.120 mil = 9,600 sq. mil
(2.032 x 3.048mm = 6.193 sq. mm)
相關(guān)PDF資料
PDF描述
TSW-102-07-G-D CONN HEADER 4POS .100" DUAL GOLD
929834-03-15-RK CONN HEADER .100 SNGL STR 15POS
929550-01-06-EU CONN HEADER .100 SNGL R/A 6POS
929834-04-11 CONN HEADER .100 SNGL STR 11POS
929834-02-18 CONN HEADER .100 SNGL STR 18POS
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
SMP04ESZ 制造商:Analog Devices 功能描述:Sample & Hold Amplifier
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