參數(shù)資料
型號(hào): SMP04EP
廠商: Analog Devices Inc
文件頁(yè)數(shù): 5/15頁(yè)
文件大?。?/td> 0K
描述: IC AMP SAMPLE HOLD CMOS 16DIP
標(biāo)準(zhǔn)包裝: 25
放大器類型: 采樣和保持
電路數(shù): 4
轉(zhuǎn)換速率: 4 V/µs
電流 - 輸入偏壓: 500nA
電壓 - 輸入偏移: 2500µV
電流 - 電源: 4mA
電流 - 輸出 / 通道: 1.2mA
電壓 - 電源,單路/雙路(±): 5 V ~ 12 V,±2.5 V ~ 6 V
工作溫度: -40°C ~ 85°C
安裝類型: 通孔
封裝/外殼: 16-DIP(0.300",7.62mm)
供應(yīng)商設(shè)備封裝: 16-PDIP
包裝: 管件
SMP04
–13–
REV. D
D/A CONVERTER DEGLITCHER
Most D/A converters output an appreciable amount of glitch
energy during a transition from one code to another. The glitch
amplitude can range from several millivolts to hundreds of milli-
volts. This may become unacceptable in many applications. By
selectively delaying the DAC’s output transition, the SMP04
can be used to smooth the output waveform. Figure 25 shows
the schematic diagram of such a deglitcher circuit. Two simple
logic gates (an OR and a NAND gate) provide the proper timing
sequence for the DAC
WR strobe and the S/H control signal to
the SMP04. In this example a linear ramp signal is generated by
feeding the most significant eight bits of the 10-bit binary
counter to the DAC. The two least significant bits are used to
produce the delayed
WR strobe and the S/H control signals.
Referring to Figure 26a, new data to the DAC input is set up at
the
S/H’s falling edge, but the DAC output does not change
until a
WR strobe goes active. During this period, the SMP04 is
in a sample mode whose output tracks the DAC output. When
S/H goes HIGH, the current DAC output voltage is held by the
SMP04. After 1.2
s settling, the WR strobe goes LOW to allow
the DAC output to change. Any glitch that occurs at the DAC
output is effectively blocked by the SMP04. As soon as the
WR
strobe goes HIGH, the digital data is latched; at the same time
the
S/H goes LOW, allowing the SMP04 to track to the new
DAC output voltage.
Figure 26b shows the deglitching operation. The top trace
shows the DAC output during a transition, while the bottom
trace shows the deglitched output of the SMP04.
1/4 SMP04
10-BIT
COUNTER
CLOCK
GENERATOR
DB2–DB9
DB0
DEGLITCH LOGIC
1/4 AD7432
1/4 AD7400
A1
A0
VDD
VREF
OUT
DAC C
OUT
1/4 DAC8426
VSS
AGND
DGND WR
+5V
+15V
1 F
AGND
0.1 F
0.1 F–1 F CERAMIC
VOUT
+15V
DGND
S/H
DB9
DB2
VDD
VSS
LSB
MSB
VIN
DIGITAL
RETURN
ANALOG
RETURN
DB1
Figure 25. DAC Deglitcher
1 s
5V
DB0
DB1
WR
S/H
a.
1 s
50m
DLY
627.4 s
b.
Figure 26. (a) Shows the Logic Timing of the Deglitcher.
The Top Two Traces Are the Two Least Significant Bits,
DB0 and DB1, Respectively. These Are Used to Generate
the
WR and S/H Signals Which Are Shown in the Bottom
Two Traces. (b) Shows the Typical Glitch Amplitude of a
DAC (Top Trace) and the Deglitched Output of the AMP04
(Bottom Trace).
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