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參數(shù)資料
| 型號： | SMM764FCR2 |
| 廠商： | Summit Microelectronics, Inc. |
| 英文描述： | Four-Channel Active DC Output Controller, Monitor, Marginer and Sequencer with Sequence-Link⑩ |
| 中文描述： | 四通道有源直流輸出控制器，監(jiān)視器，Marginer和音序器的序列連接⑩ |
| 文件頁數(shù)： | 9/33頁 |
| 文件大?。?/td> | 392K |
| 代理商： | SMM764FCR2 |
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SMM764
Preliminary Information
Summit Microelectronics, Inc
2098 1.1 6/29/2005
9
DC OPERATING CHARACTERISTICS (CONTINUED)
(Over recommended operating conditions, unless otherwise noted. All voltages are relative to GND.)
Symbol
Parameter
Notes
Min
0.8 x
Typ
Max
Unit
Internally regulated to 3.6V
VDD_CAP
V
V
IH
Input high voltage (MR#, SDA,
SCL, PWR_ON, SEQ_LINK,
FS#)
Internally regulated to 5.5V
0.7 x
VDD_CAP
V
Internally regulated to 3.6V
0.2 x
VDD_CAP
V
V
IL
Input low voltage (MR#, SDA,
SCL, PWR_ON, SEQ_LINK,
FS#)
3
Internally regulated to 5.5V
0.3 x
VDD_CAP
V
V
OL
Open drain outputs (RST#,
FS#, PWR_ON, HEALTHY,
FAULT#, PUPx, SEQ_LINK)
I
SINK
= 1mA
0
0.4
V
I
OL
Output low current
Note – Total I
SINK
from all PUPx pins
should not exceed 3mA or ADOC
ACC
specification will be affected
VM pin
VM, AIN1/AIN2 pins
Commercial temp range
Industrial temp range
0
1.0
mA
V
SENSE
V
MONITOR
Positive sense voltage
Monitor threshold step size
+0.3
-3
-5
VDD_CAP
V
mV
o
C
o
C
5
+3
+5
t
SA
Internal temperature sensor
accuracy
t
MONITOR
Temperature threshold step
size
Internal 1.25 VREF output
voltage
Internal VREF temperature
coefficient
Internal temp sensor
0.25
o
C
VREF
1.24
1.25
1.26
V
–40
°
C to +85
°
C
0
°
C to +70
°
C
-0.25
-0.15
+0.25
+0.15
%
%
TC
VREF ACC Internal VREF accuracy
-0.4
+0.4
%
Ext VREF
External VREF voltage range
External VREF=1.25V,
±0.1%, total PUPx I
SINK
<
3ma, V
SENSE
<
3.5V
External VREF=1.25V,
±0.1%, total PUPx I
SINK
<
3ma, V
SENSE
>
3.5V
Internal VREF=1.25V, total
PUPx I
SINK
< 3ma
VDD_CAP voltage at which
the PUP, RST#, HEALTHY
and FAULT#, FS#, PWR_ON
SEQ_LINK
,
outputs are valid
VDD_CAP rising
VDD_CAP falling
0.5
VDD_CAP
V
-0.2
0.1
+0.2
%
-0.5
0.3
+0.5
%
ADOC
ACC
ADOC (Active DC Output
Control)/margin accuracy
-0.5
0.3
+0.5
%
V
OUT_VALID
Minimum output valid voltage
1
V
2.6
2.5
V
V
UVLO
UVLO (Under Voltage Lockout)
threshold
4
ote 1 – Range depends on internal regulator set to 3.6V or 5.5V see 12VIN specification.
Note 2 – See Application Note 37 which describes the type of capacitors to use to obtain minimum leakage.
Note 3 – All logic levels are derived with respect to the voltage present on VDD_CAP, when supplied from the VDD input VDD_CAP is equal to
VDD, under no load.
Note 4 – (100mV typ Hysteresis)
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相關(guān)代理商/技術(shù)參數(shù) |
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| SMM764FCR3 | 制造商:SUMMIT 制造商全稱:SUMMIT 功能描述:Four-Channel Active DC Output Controller, Monitor, Marginer and Sequencer with Sequence-Link⑩ |
| SMM764FCR4 | 制造商:SUMMIT 制造商全稱:SUMMIT 功能描述:Four-Channel Active DC Output Controller, Monitor, Marginer and Sequencer with Sequence-Link⑩ |
| SMM764FCR5 | 制造商:SUMMIT 制造商全稱:SUMMIT 功能描述:Four-Channel Active DC Output Controller, Monitor, Marginer and Sequencer with Sequence-Link⑩ |
| SMM764FCR6 | 制造商:SUMMIT 制造商全稱:SUMMIT 功能描述:Four-Channel Active DC Output Controller, Monitor, Marginer and Sequencer with Sequence-Link⑩ |
| SMM764FCR7 | 制造商:SUMMIT 制造商全稱:SUMMIT 功能描述:Four-Channel Active DC Output Controller, Monitor, Marginer and Sequencer with Sequence-Link⑩ |
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