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參數(shù)資料
| 型號(hào)： | SMM105NER04 |
| 廠商： | Summit Microelectronics, Inc. |
| 英文描述： | Single-Channel Supply Voltage Marginer and Active DC Output Controller |
| 中文描述： | 單通道供電電壓Marginer和有源直流輸出控制器 |
| 文件頁數(shù)： | 4/21頁 |
| 文件大?。?/td> | 384K |
| 代理商： | SMM105NER04 |
SMM105
Preliminary Information
Summit Microelectronics, Inc
2068 1.8 09/20/05
4
PIN DESCRIPTIONS
QFN
Pad
Number
Ultra
CSP
TM
Ball
Number
Pin
Type
Pin Name
Pin Description
28
1
2
4
6
A3
A1
A2
B2
C2
DATA
CLK
I
I
I
SDA
SCL
A2
A1
A0
I
2
C Bi-directional data line
I
2
C clock input.
The address pins are biased either to VDD_CAP or GND. When
communicating with the SMM105 over the 2-wire bus these pins
provide a mechanism for assigning a unique bus address.
Write Protect active low input. When asserted, writes to the
configuration registers and general purpose EE are not allowed.
External capacitor input used to filter the VM input.
8
E1
I
WP#
10
E2
CAP
FILT_CAP
18
C5
CAP
TRIM_CAP
External capacitor input used for Active Control and margining.
Output voltage used to control and/or margin converter voltages.
Connect to the converter trim input.
Voltage monitor input. Connect to the DC-DC converter positive
sense line or its’ +Vout pin.
Voltage reference input used for DC output control and margining.
VREF_CNTL can be programmed to output the internal 1.25V
reference. Pin should be left open if using VREF internal
Power supply of the part.
Ground of the part. The SMM105 ground pin should be connected
to the ground of the device under control or to a star point ground.
PCB layout should take into consideration ground drops.
12V power supply input internally regulated to either 3.6V or 5.5V.
When using the 3.6V internal regulator option, the 12VIN input can
be as low as 8V. It can be as high as 15V using the 5.5V internal
regulator.
Programmable active high/low input. The START input is used
solely for enabling Active Control and/or margining. There is also
a programmable start delay time, T
START
to delay ADOC/Margin
control.
Programmable active high/low open drain output indicates that VM
is at its set point. When programmed as an active high output,
READY can also be used as an input. When pulled low, it will latch
the state of the comparator inputs.
External capacitor input used to filter the internal supply rail.
COMP1 and COMP2 are high impedance inputs, each connected
internally to a comparator and compared against the VREF_CNTL
input. Each comparator can be independently programmed to
monitor for UV or OV. The monitor level is set externally with a
resistive voltage divider.
When either of the COMP1 or COMP2 inputs are in fault the open-
drain FAULT# output will be pulled low. A configuration option
exists to disable the FAULT# output while the device is margining.
20
B5
O
TRIM
14
E4
I
VM
9
D2
I
VREF_CNTL
21
B4
PWR
VDD
7
D1
GND
GND
22
A5
PWR
12VIN
3
B1
I
START
5
C1
I/O
READY
23
A4
CAP
VDD_CAP
19
C4
I
COMP1
12
E3
I
COMP2
11
D3
O
FAULT#
13,15,16
17,24-27
B3,C3,
D4,D5,
E5
NC
NC
No Connect. Leave floating; do not connect anything to the NC
pins.
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| SMM105NER05 | 制造商:SUMMIT 制造商全稱:SUMMIT 功能描述:Single-Channel Supply Voltage Marginer and Active DC Output Controller |
| SMM105NNCR00 | 制造商:SUMMIT 制造商全稱:SUMMIT 功能描述:Single-Channel Supply Voltage Marginer and Active DC Output Controller |
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| SMM105NNCR04 | 制造商:SUMMIT 制造商全稱:SUMMIT 功能描述:Single-Channel Supply Voltage Marginer and Active DC Output Controller |
| SMM105NNCR05 | 制造商:SUMMIT 制造商全稱:SUMMIT 功能描述:Single-Channel Supply Voltage Marginer and Active DC Output Controller |
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