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參數(shù)資料
| 型號： | SML2120N |
| 廠商： | Summit Microelectronics, Inc. |
| 英文描述： | Programmable Adaptive Laser Power Controller with Dual Lookup Tables |
| 中文描述： | 可編程控制器自適應(yīng)激光功率雙查找表 |
| 文件頁數(shù)： | 13/32頁 |
| 文件大小： | 1196K |
| 代理商： | SML2120N |
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SML2120
Applications Information
Summit Microelectronics
2066 6.3 1/22/04
13
Bits 7 and 6 are read-only bits that indicate the offending
channel and limit, respectively, during an alert condition.
Bits 3:0 are I/O's that indicate the status of the device when
read out, and affect operation of the device when written to.
Bit 3 represents the state of the ALERT# output; when this
bit is high, the ALERT# output is asserted. Writing a zero to
this bit will de-assert the ALERT# output. Bits 2 and 1
represent the state of the Auto-Monitor and Output Enable
functions, respectively. On power-up, these functions are
controlled by the appropriate pin, AM# or ENA#; however,
the state of either pin may be overridden by writing to the
selected bit of the status register. Bit 0 controls the write
protect status of the device; no data may be changed until
this bit is cleared.
Dual Voltage Operation
The SML2120 was designed to operate with a single-ended
supply (i.e. 3.3V or 5V), or in a dual voltage environment of
–5.2V, 0V, and +3.3V. It is common for many lasers to be
driven off the –5.2V rail, while the interface runs on the
positive supply. The SML2120 runs entirely between VDD
and VSS, with the exception of the digital interface pins
(pins 1-6) and three analog monitor pins (26-28), which are
driven between VHI and VLOW. Table 3 details the different
modes of operation. In all cases, current outputs are
sourced from VDD and sink to VSS.
Analog Monitor Outputs
There are three analog monitor outputs on the SML2120
that provide a continuous measure of the critical parameters
in the system. The POWERMON output reflects the state of
the APC loop, which is an indirect measure of the laser
power output. The TEMPMON output has different
characteristics depending on which input has been selected
as the temperature pin. If the ADC input for either LUT0 or
LUT1 is selected to be from the THERMISTOR pin, then the
TEMPMON output is a level-shifted and amplified version of
the THERMISTOR input. Otherwise, the TEMPMON output
is generated based on the voltage on the EXT_TEMP pin.
The BIASMON output indicates the instantaneous bias
current. All three of these outputs are level-shifted up to the
VHIGH/VLOW rail as described by the following equations:
V
POWERMON
- V
LOW
= (V
C1
- V
SS
)
V
TEMPMON
- V
LOW
= (V
EXT_TEMP
- V
SS
) or
25 * ((V
THERMISTOR
- V
SS
) - 0.1)
V
BIASMON
- V
LOW
= 2 * I
BIAS
/I
BIASMAX
Serial Interface
The SML2120 uses the industry standard I
2
C, 2-wire serial
interface. This interface provides access to the status
registers, ADC, general purpose E
2
PROM, configuration
registers and LUT tables according to Table 4. Associated
with the interface are two address pins (A2 and A1), which
allow up to four devices on the same bus.
Table 2. Status Register
Slave Address 1001, Word Address 00Fh
Bit
I/O
Description
7
Output
Alert Channel
6
Output
Alert Limit (Hi/Low)
5:4
-
Unused
3
I/O
Alert
2
I/O
Auto-Monitor
1
I/O
Output Enable
0
I/O
Write Protect
Table 3. Voltage Supply Modes
Pin
Single
Supply
Single
Supply
Dual Supply
VDD
3.0V to 3.6V
4.5V to 5.5V
0V
VSS
0V
0V
-5.5V to
-4.9V
VHI
3.0V to 3.6V
4.5V to 5.5V
3.0V to
3.6V
VLOW
0V
0V
0V
Digital
Interface
0V TO 3.6v
0V TO 5.5V
0V to 3.6V
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