
Applications Information
SML2120
12
2066 6.3 1/22/04
Summit Microelectronics
Thermistor Interface
The SML2120 has circuits built-in to help facilitate using a
thermistor to measure laser temperature. The VBRIDGE pin
provides a .2V output reference to drive half of a bridge
circuit that includes the thermistor and one other external
resistor. The other half of the bridge is internal to the device.
The external components are placed between the
VBRIDGE, THERMISTOR, and VSS pins as shown in
Figure 3.
Programmable Current Outputs
There are two fully independent, programmable current
outputs on the SML2120: ILU0 and ILU1. The output
polarity (source or sink current), as well as the upper and
lower current limit may be individually programmed to meet
varying output requirements. The upper and lower limits for
each channel may be set between 0 and 2.5 mA in 256
steps. These limits can help prevent damage to
components receiving the output current, and they increase
resolution in the desired operating range. The final output
current is determined by an 8-bit DAC that ranges between
the upper and lower current limits (refer to Figure 7). A
power-up register determines the initial DAC setting; during
Auto-Monitor operation, data read out of the array is loaded
into the DAC register to determine the output current.
Figure 7. Independent Lookup Tables
Burst Mode
The SML2120 is designed to work in applications that
require burst mode operation. The output currents (ILU0,
ILU1 and BIAS) may be switched on and off by using the
ENA# pin. In applications that require very high speed
operation, the VBURST pin may be used as a ballast load
for the BIAS current. When ENA# is de-asserted, all current
that was flowing through the BIAS output is diverted to the
VBURST pin. For optimal performance, the load attached to
VBURST should closely resemble the load of the laser in
order to keep internal nodes biased at the correct levels.
Additionally, the ENA# pin should be configured for "FAST
MODE" by setting Config Reg 15, Bit 7 high. This setting
increases the throughput of the enabling signal by
eliminating noise filters on the input; this setting also
eliminates the VHIGH/VLOW level shifter. Thus, when using
the ENA# pin in FAST MODE, the input levels need to range
between VDD and VSS, rather than VHIGH and VLOW.
(Applicable only in dual voltage systems.)
E
2
PROM
The SML2120 contains 6k bits of user-accessible E
2
PROM
memory. Each LUT is comprised of 2k bits arranged as 256
words by 8 bits. LUT0 occupies addresses 000h - 0FFh and
LUT1 occupies addresses 100h - 1FFh, both using the I
2
C
slave address of 1011. A third 2k block of E
2
PROM is
available to the user as a general-purpose memory. This
block is accessed via slave address 1010, memory
addresses 000h - 0FFh.
Device configuration information is stored in 16 non-volatile
registers located at addresses 100h - 10Fh, also under the
slave address 1010. Note that the user may program the
device to prevent any further writes to this configuration
space.
Refer to the "Configuration Register Description" section
below for details of the available configuration settings.
Refer to "I
2
C Interface" section for further details and
examples of communicating with the SML2120 over the I
2
C
bus.
Status Register
The Status register is a volatile register that allows the user
to control and receive feedback from the device, accessible
using the 1001 slave address at memory address 00Fh.
Table 2 describes the status byte:
Lookup
Table
0
DAC
256x8
EPROM
High Range
Low Range
(register 10)
Power Up
Register
(register 8)
(register 11)
Source
Current
Current
Sink
(register 14, bit 6)
Polarity
Select
ILU0
Lookup
Table
1
DAC
256x8
EPROM
High Range
Low Range
(register 12)
Power Up
Register
(register 9)
(register 13)
Source
Current
Current
Sink
(register 14, bit 7)
Polarity
Select
ILU1
ILU0 Lookup
ILU1 Lookup