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參數(shù)資料
| 型號： | SML2108F |
| 廠商： | Summit Microelectronics, Inc. |
| 英文描述： | Laser Diode Adaptive Power Controller |
| 中文描述： | 激光二極管自適應功率控制器 |
| 文件頁數(shù)： | 14/21頁 |
| 文件大?。?/td> | 465K |
| 代理商： | SML2108F |
14
SML2108
PRELIMINARY
2053 2.2 11/07/00
SUMMIT MICROELECTRONICS, Inc.
Start and Stop Conditions
Both Data and Clock lines remain high when the bus is not
busy. Data transfer between devices may be initiated with
a Start condition only when SCL and SDA are high. A high-
to-low transition of the Data line while the Clock line is high
is defined as a Start condition. A low-to-high transition of
the Data line while the Clock line is high is defined as a Stop
condition. See Figure 9.
Protocol
The protocol defines any device that sends data onto the
bus as a Transmitter, and any device that receives data as
a Receiver. The device controlling data transmission is
called the Master, and the controlled device is called the
Slave. In all cases the Summit Microelectronic devices
are slave devices, since they never initiate any data
transfers.
Acknowledge
Data is always transferred in 8-Bit bytes. Acknowledge
(ACK) is used to indicate a successful data transfer. The
Transmitting device will release the bus after transmitting
eight bits. During the ninth clock cycle the Receiver will
pull the SDA line low to Acknowledge that it received the
eight bits of data (See Figure 10). The termination of a
Master Read sequence is indicated by a non-Acknowl-
edge (NACK), where the Master will leave the Data line
high.
Figure 9. I
2
C Start and Stop Timing
Figure 10. Acknowledge Timing
In the case of a Read from a Summit part, when the last
byte has been transferred to the Master, the Master will
leave the Data line high for a NACK. This will cause the
Summit part to stop sending data, and the Master will issue
a Stop on the clock pulse following the NACK.
In the case of a Write to a Summit part the Master will send
a Stop on the clock pulse after the last Acknowledge. This
will indicate to the Summit part that it should begin its
internal non-volatile write cycle.
Read and Write
The first byte from a Master is always made up of a seven
bit Slave address and the Read/Write bit. The R/W bit tells
the Slave whether the Master is reading Data from the bus
or writing Data to the bus (1 = read, 0 = write). The first four
of the seven address bits are called the Device Type
Identifier (DTI). The DTI for the SML2108 is 1010. The
next three bits are not used in the SML2108 (See Figure
11). The SML2108 will issue an Acknowledge after
recognizing a Start condition and its DTI.
In the read mode the SML2108 transmits eight bits of data,
then releases the SDA line, and monitors the line for an
Acknowledge signal. If an Acknowledge is detected, and
no Stop condition is generated by the Master, the
SML2108 will continue to transmit data. If an Acknowl-
edge is not detected (NACK) the SML2108 will terminate
further data transmission. See Figure 12.
Figure 11. Typical Master Address Byte Transmission
2053 Fig09
SCL
SDA In
START
Condition
STOP
Condition
SCL
SDA
Trans
SDA
Rec
1
2
3
8
9
ACK
2053 Fig10
SCL
SDA
1
2
3
8
9
4
5
6
7
1
0
1
R/W
0
x
x
x
ACK
2053 Fig11
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