參數(shù)資料
型號: SMH4814SCR03
廠商: Summit Microelectronics, Inc.
元件分類: 基準電壓源/電流源
英文描述: Dual Feed Active-ORing Programmable Hot Swap Controller
中文描述: 雙飼料有源ORing提供可編程熱插拔控制器
文件頁數(shù): 10/44頁
文件大?。?/td> 935K
代理商: SMH4814SCR03
SMH4814
Preliminary Information
Summit Microelectronics, Inc
2080 2.0 07/21/05
10
I
2
C 2-WIRE SERIAL INTERFACE AC OPERATING CHARACTERISTICS – 100/400kHz
Over recommended operating conditions, unless otherwise noted. All voltages are relative to V
SS
. See Figure 4
Timing Diagram.
100kHz
Typ
400kHz
Typ
Symbol
Description
Conditions
Min
0
4.7
4.0
Max
100
Min
0
1.3
0.6
Max
400
Units
KHz
f
SCL
t
LOW
t
HIGH
SCL Clock Frequency
Clock Low Period
Clock High Period
μ
s
μ
s
t
BUF
Bus Free Time
Before New Transmission
-
Note
1/
SCL low to valid
SDA (cycle n)
SCL low (cycle n+1)
to SDA change
Note
1/
4.7
1.3
μ
s
t
SU:STA
t
HD:STA
t
SU:STO
Start Condition Setup Time
Start Condition Hold Time
Stop Condition Setup Time
4.7
4.0
4.7
0.6
0.6
0.6
μ
s
μ
s
μ
s
t
AA
Clock Edge to Data Valid
0.2
3.5
0.2
0.9
μ
s
t
DH
Data Output Hold Time
0.2
0.2
μ
s
t
R
t
F
t
SU:DAT
t
HD:DAT
TI
t
WR
SCL and SDA Rise Time
SCL and SDA Fall Time
Data In Setup Time
Data In Hold Time
Noise Filter SCL and SDA
Write Cycle Time
1000
300
5
1000
300
5
ns
ns
ns
ns
ns
ms
Note
1/
250
0
150
0
Noise suppression
Memory Array
100
100
Note: 1/ - Guaranteed by Design.
t
R
t
F
t
HIGH
t
LOW
t
SU:SDA
t
HD:SDA
t
SU:DAT
t
HD:DAT
t
SU:STO
t
BUF
t
DH
t
AA
SCL
SDA
(IN)
SDA
(OUT)
t
WR (For Write Operation Only)
Figure 4 . Basic I
2
C serial interface timing diagram for the Bus Interface and Memory timing. The table above
lists the AC timing parameters. One bit of data is transferred during each clock pulse. Note that data must
remain stable when the clock is high.
TIMING DIAGRAMS
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