
SMH4814 
PIN DESCRIPTION (CONTINUED) 
Preliminary Information 
Summit Microelectronics, Inc 
2080  2.0  07/21/05 
5 
Pin No. 
QFN 
Pin Type 
Name 
Description 
18 
I 
FEED
A
Connect to the -48V 'A' feed using a series 100k resistor.  The voltage on 
this pin is compared with the voltage on the FEED
B
 pin internally by the 
supply arbitration logic to determine which voltage will be used.   
The DRAIN SENSE input monitors the voltage at the drain of the external 
power MOSFET switch with respect to VSS.  An internal 10μA source pulls 
the DRAIN SENSE signal towards the 5V_CAP level.  DRAIN SENSE must 
be held below 2.5V to enable the PUP
X
 outputs. 
External capacitor input used to filter the device’s internal operating supply. 
Also a hold Capacitor to sequence down and to filter any power glitches. 
The VGATE_HS output activates an external power MOSFET switch. This 
signal controls inrush current by modulating the gate of the Hot Swap 
MOSFET device. It supplies a programmable current output which allows 
easy adjustment of the MOSFET turn-on slew rate. 
This pin controls the gate of the active FET on FEED
B
. 
This pin controls the gate of the active FET on FEED
A
This is the positive supply input.  An internal shunt regulator limits the 
voltage on this pin to approximately 12V with respect to V
SS
.  A resistor 
must be placed in series with the V12 pin to limit the regulator current (R
D
 in 
the application schematics). 
Active-high, logic level input that can be used to indicate when the converter 
controlled by PUP
D
 is fully powered.
A hold-off timer allows the secondary 
side (which is not powered up initially) to control shut down via an opto-
isolator. See Figures 5 and 6.  
Active-high, logic level input that can be used to indicate when the converter 
controlled by PUP
C
 is fully powered.
A hold-off timer allows the secondary 
side (which is not powered up initially) to control shut down via an opto-
isolator.  See Figures 5 and 6. 
Active-high, logic level input that can be used to indicate when the converter 
controlled by PUP
B
 is fully powered.
A hold-off timer allows the secondary 
side (which is not powered up initially) to control shut down via an opto-
isolator. See Figures 5 and 6.  
Active-high, logic level input that can be used to indicate when the converter 
controlled by PUP
A
 is fully powered.
A hold-off timer allows the secondary 
side (which is not powered up initially) to control shut down via an opto-
isolator. See Figures 5 and 6.  
19 
I 
DRAIN 
SENSE 
20 
O 
5V_CAP 
21 
O 
VGATE_HS 
22 
O 
VGATE
B
VGATE
A
V12 
23 
O 
24 
PWR 
25 
I 
FB
D
26 
I 
FB
C
27 
I 
FB
B
28 
I 
FB
A