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參數(shù)資料
| 型號(hào)： | SM320VC33HFGM150 |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 數(shù)字信號(hào)處理 |
| 英文描述： | 32-BIT, 75 MHz, OTHER DSP, CQFP164 |
| 封裝： | NCTB, CERAMIC, MO-113AA, QFP-164 |
| 文件頁數(shù)： | 35/56頁 |
| 文件大?。?/td> | 669K |
| 代理商： | SM320VC33HFGM150 |
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SM320VC33, SMJ320VC33
DIGITAL SIGNAL PROCESSOR
SGUS034E - FEBRUARY 2001 - REVISED OCTOBER 2002
40
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251-1443
interrupt response timing
The following table defines the timing parameters for the INTx signals.
timing requirements for INT3-INT0 response (see Figure 28)
MIN
NOM
MAX
UNIT
tsu(INT-H1L)
Setup time, INT3- INT0 before H1 low
4*
ns
th(H1L-INT)
Hold time, INT3- INT0 after H1 low
0
ns
tw(INT)
Pulse duration, interrupt to ensure only one interrupt
P + 5*
1.5P
2P - 5*
ns
* Not production tested
P = tc(H)
The interrupt (INTx) pins are synchronized inputs that can be asserted at any time during a clock cycle. The
TMS320C3x interrupts are selectable as level- or edge-sensitive. Interrupts are detected on the falling edge of
H1. Therefore, interrupts must be set up and held to the falling edge of the internal H1 for proper detection. The
CPU and DMA respond to detected interrupts on instruction-fetch boundaries only.
For the processor to recognize only one interrupt when level mode is selected, an interrupt pulse must be set
up and held such that a logic-low condition occurs for:
D A minimum of one H1 falling edge
D No more than two H1 falling edges
D Interrupt sources whose edges cannot be specified to meet the H1 falling edge setup and hold times must
be further restriced in pulse width as defined by tw(INT) (parameter 51) in the table above.
When EDGEMODE=1, the falling edge of the INT0-INT3 pins are detected using synchronous logic (see
Figure 7). The pulse low and high time should be two CPU clocks or greater.
The TMS320C3x can set the interrupt flag from the same source as quickly as two H1 clock cycles after it has
been cleared.
If the specified timings are met, the exact sequence shown in Figure 28 occurs; otherwise, an additional delay
of one clock cycle is possible.
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| SM320VC5409GGU10EP | 功能描述:數(shù)字信號(hào)處理器和控制器 - DSP, DSC Fxd-pt Dig Sig Proc Mil enhanced RoHS:否 制造商:Microchip Technology 核心:dsPIC 數(shù)據(jù)總線寬度:16 bit 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:2 KB 最大時(shí)鐘頻率:40 MHz 可編程輸入/輸出端數(shù)量:35 定時(shí)器數(shù)量:3 設(shè)備每秒兆指令數(shù):50 MIPs 工作電源電壓:3.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-44 安裝風(fēng)格:SMD/SMT |
| SM320VC5416-EP | 制造商:TI 制造商全稱:Texas Instruments 功能描述:SM320VC5416-EP Fixed-Point Digital Signal Processor |
| SM320VC5416GGU16EP | 功能描述:數(shù)字信號(hào)處理器和控制器 - DSP, DSC Fxd-pt Dig Sig Proc Mil enhanced RoHS:否 制造商:Microchip Technology 核心:dsPIC 數(shù)據(jù)總線寬度:16 bit 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:2 KB 最大時(shí)鐘頻率:40 MHz 可編程輸入/輸出端數(shù)量:35 定時(shí)器數(shù)量:3 設(shè)備每秒兆指令數(shù):50 MIPs 工作電源電壓:3.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-44 安裝風(fēng)格:SMD/SMT |
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