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參數(shù)資料
| 型號(hào)： | SM320C6414DGADW60 |
| 廠(chǎng)商： | TEXAS INSTRUMENTS INC |
| 元件分類(lèi)： | 數(shù)字信號(hào)處理 |
| 英文描述： | 64-BIT, 75 MHz, OTHER DSP, CPGA570 |
| 封裝： | 33 X 33 MM, CERAMIC, FCPGA-570 |
| 文件頁(yè)數(shù)： | 9/134頁(yè) |
| 文件大?。?/td> | 1997K |
| 代理商： | SM320C6414DGADW60 |
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SMJ320C6414, SMJ320C6415, SMJ320C6416
FIXEDPOINT DIGITAL SIGNAL PROCESSORS
SGUS050A JANUARY 2004 REVISED MARCH 2004
106
POST OFFICE BOX 1443
HOUSTON, TEXAS 772511443
RESET TIMING (CONTINUED)
ECLKOUT2
17
14
1
CLKOUT4
CLKOUT6
RESET
ECLKIN
Low Group
Z Group§
Boot and Device
Configuration Inputs§
16
15
3
2
10
8
EMIF Z Group§
EMIF High Group
EMIF Low Group
11
9
7
6
13
12
ECLKOUT1
5
4
These C64x devices have two EMIFs (EMIFA and EMIFB). All EMIFA signals are prefixed by an “A” and all EMIFB signals are prefixed by a
“B”. Throughout the rest of this document, in generic EMIF areas of discussion, the prefix “A” or “B” may be omitted [e.g., ECLKIN, ECLKOUT1,
and ECLKOUT2].
EMIF Z group consists of:
AEA[22:3], BEA[20:1], AED[63:0], BED[15:0], CE[3:0], ABE[7:0], BBE[1:0], ARE/SDCAS/SADS/SRE,
AWE/SDWE/SWE, and AOE/SDRAS/SOE, SOE3, ASDCKE, and PDT.
EMIF high group consists of: AHOLDA and BHOLDA (when the corresponding HOLD input is high)
EMIF low group consists of:
ABUSREQ and BBUSREQ; AHOLDA and BHOLDA (when the corresponding HOLD input is low)
Low group consists of:
XSP_CS, CLKX2/XSP_CLK, and DX2/XSP_DO; all of which apply only when PCI EEPROM (BEA13)
is enabled (with PCI_EN = 1 and MCBSP2_EN = 0). Otherwise, the CLKX2/XSP_CLK and DX2/XSP_DO
pins are in the Z group. For more details on the PCI configuration pins, see the Device Configurations section
of this data sheet.
Z group consists of:
HD[31:0]/AD[31:0], CLKX0, CLKX1/URADDR4, CLKX2/XSP_CLK, FSX0, FSX1/UXADDR3, FSX2, DX0,
DX1/UXADDR4, DX2/XSP_DO, CLKR0, CLKR1/URADDR2, CLKR2, FSR0, FSR1/UXADDR2, FSR2,
TOUT0, TOUT1, TOUT2, GP[8:0], GP10/PCBE3, HR/W/PCBE2, HDS2/PCBE1, PCBE0, GP13/PINTA,
GP11/PREQ, HDS1/PSERR, HCS/PPERR, HCNTL1/PDEVSEL, HAS/PPAR, HCNTL0/PSTOP,
HHWIL/PTRDY (16-bit HPI mode only), HRDY/PIRDY, HINT/PFRAME, UXDATA[7:0], UXSOC, UXCLAV,
and URCLAV.
§ If BEA[20:13, 11, 7] and HD5/AD5 pins are actively driven, care must be taken to ensure no timing contention between parameters 6, 7, 14, 15,
16, and 17.
Boot and Device Configurations Inputs (during reset) include: EMIFB address pins BEA[20:13, 11, 7] and HD5/AD5.
The PCI_EN pin must be driven valid at all times and the user must not switch values throughout device operation.
The MCBSP2_EN pin must be driven valid at all times and the user can switch values throughout device operation.
Figure 37. Reset Timing
相關(guān)PDF資料 |
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| SMJ34010-50FDM | GRAPHICS PROCESSOR, CQCC68 |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SM320C6414-EP | 制造商:TI 制造商全稱(chēng):Texas Instruments 功能描述:FIXED-POINT DIGITAL SIGNAL PROCESSORS |
| SM320C6415DGADW60 | 制造商:Texas Instruments 功能描述:DSP Fixed-Point 32-Bit 600MHz 4800MIPS 570-Pin FCPGA Tray |
| SM320C6416DGADW60 | 制造商:TI 制造商全稱(chēng):Texas Instruments 功能描述:FIXD-POINT DIGITAL SIGNAL PROCESSORS |
| SM320C6424GDUQ6EP | 功能描述:數(shù)字信號(hào)處理器和控制器 - DSP, DSC EP Fixed-Pt Dig Signal Proc RoHS:否 制造商:Microchip Technology 核心:dsPIC 數(shù)據(jù)總線(xiàn)寬度:16 bit 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:2 KB 最大時(shí)鐘頻率:40 MHz 可編程輸入/輸出端數(shù)量:35 定時(shí)器數(shù)量:3 設(shè)備每秒兆指令數(shù):50 MIPs 工作電源電壓:3.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-44 安裝風(fēng)格:SMD/SMT |
| SM320C6455BGTZEP | 功能描述:數(shù)字信號(hào)處理器和控制器 - DSP, DSC Enh Product Fixed- Pt Dig Signal Proc RoHS:否 制造商:Microchip Technology 核心:dsPIC 數(shù)據(jù)總線(xiàn)寬度:16 bit 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:2 KB 最大時(shí)鐘頻率:40 MHz 可編程輸入/輸出端數(shù)量:35 定時(shí)器數(shù)量:3 設(shè)備每秒兆指令數(shù):50 MIPs 工作電源電壓:3.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-44 安裝風(fēng)格:SMD/SMT |
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