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參數(shù)資料
| 型號： | SM320C6201BW14 |
| 廠商： | Texas Instruments, Inc. |
| 元件分類： | 數(shù)字信號處理 |
| 英文描述： | FLOATING-POINT DIGITAL SIGNAL PROCESSOR |
| 中文描述： | 浮點數(shù)字信號處理器 |
| 文件頁數(shù)： | 43/64頁 |
| 文件大?。?/td> | 939K |
| 代理商： | SM320C6201BW14 |
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SGUS030B
–
APRIL 2000
–
REVISED MAY 2001
43
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251
–
1443
RESET TIMING
timing requirements for reset (see Figure 25)
NO.
’
C6701-14
’
C6701-16
UNIT
MIN
MAX
1
tw(RESET)
Width of the RESET pulse (PLL stable)
*10
CLKOUT1
cycles
μ
s
Width of the RESET pulse (PLL needs to sync up)
*250
This parameter applies to CLKMODE x1 when CLKIN is stable and applies to CLKMODE x4 when CLKIN and PLL are stable.
*This parameter is not tested.
This parameter only applies to CLKMODE x4. The RESET signal is not connected internally to the clock PLL circuit. The PLL, however, may
need up to 250
μ
s to stabilize following device powerup or after PLL configuration has been changed. During that time, RESET must be asserted
to ensure proper device operation. See the
clock PLL
section for PLL lock times.
switching characteristics during reset
§
(see Figure 25)
NO.
PARAMETER
’
C6701-14
’
C6701-16
UNIT
MIN
MAX
2
tR(RESET)
Response time to change of value in RESET signal
*1
CLKOUT1
cycles
3
td(CKO1H-CKO2IV)
td(CKO1H-CKO2V)
td(CKO1H-SDCLKIV)
td(CKO1H-SDCLKV)
td(CKO1H-SSCKIV)
td(CKO1H-SSCKV)
td(CKO1H-LOWIV)
td(CKO1H-LOWV)
td(CKO1H-HIGHIV)
td(CKO1H-HIGHV)
td(CKO1H-ZHZ)
td(CKO1H-ZV)
§
Low group consists of:
High group consists of:
Z group consists of:
Delay time, CLKOUT1 high to CLKOUT2 invalid
*
–
1
ns
4
Delay time, CLKOUT1 high to CLKOUT2 valid
*10
ns
5
Delay time, CLKOUT1 high to SDCLK invalid
*
–
1
ns
6
Delay time, CLKOUT1 high to SDCLK valid
*10
ns
7
Delay time, CLKOUT1 high to SSCLK invalid
*
–
1
ns
8
Delay time, CLKOUT1 high to SSCLK valid
*10
ns
9
Delay time, CLKOUT1 high to low group invalid
*
–
1
ns
10
Delay time, CLKOUT1 high to low group valid
*10
ns
11
Delay time, CLKOUT1 high to high group invalid
*
–
1
ns
12
Delay time, CLKOUT1 high to high group valid
*10
ns
13
Delay time, CLKOUT1 high to Z group high impedance
*
–
1
ns
14
Delay time, CLKOUT1 high to Z group valid
*10
ns
IACK, INUM[3:0], DMAC[3:0], PD, TOUT0, and TOUT1.
HRDY and HINT.
EA[21:2], ED[31:0], CE[3:0], BE[3:0], ARE, AWE, AOE, SSADS, SSOE, SSWE, SDA10, SDRAS, SDCAS,
SDWE, HD[15:0], CLKX0, CLKX1, FSX0, FSX1, DX0, DX1, CLKR0, CLKR1, FSR0, and FSR1.
*This parameter is not tested.
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