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參數(shù)資料
| 型號： | SM320C25-50FJM |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 數(shù)字信號處理 |
| 英文描述： | 16-BIT, 50 MHz, OTHER DSP, CQCC68 |
| 封裝： | CERAMIC, MS-004, LCC-68 |
| 文件頁數(shù)： | 13/40頁 |
| 文件大?。?/td> | 681K |
| 代理商： | SM320C25-50FJM |
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SMJ320C25, SMJ320C2550
DIGITAL SIGNAL PROCESSOR
SGUS007D – AUGUST 1988 – REVISED OCTOBER 2001
20
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
0.80 V
0.92 V
1.88 V
2.0 V
0
VIH (Min)
VIL (Max)
(a) Input
0.6 V
0.8 V
2.2 V
2.4 V
0
VOH (Min)
VOL (Max)
(b) Output
Figure 4. Voltage Reference Levels
switching characteristics over recommended operating conditions (see Note 1)
PARAMETER
SMJ320C25-50
SMJ320C25
UNIT
PARAMETER
MIN
MAX
MIN
TYP
MAX
UNIT
td(C1–S) STRB from CLKOUT1 (if STRB is present)
Q – 5
Q + 3
Q – 6
Q
Q + 6
ns
td(C2–S) CLKOUT2 to STRB (if STRB is present)
–2
5
–6
0
6
ns
tsu(A)
Address setup time before STRB low (see Note 3)
Q – 13
Q – 12
ns
th(A)
Address hold time after STRB high (see Note 3)
Q – 4
Q – 8
ns
tw(SL)
STRB low pulse duration (no wait states, see Note 4)
2Q – 5
2Q + 5
2Q – 5
2Q
2Q + 5
ns
tw(SH)
STRB high pulse duration (between consecutive cycles, see Note 4)
2Q – 5
2Q + 5
2Q – 5
2Q + 5
ns
tsu(D)W Data write setup time before STRB high (no wait states)
2Q – 17
2Q – 20
ns
th(D)W
Data write hold time from STRB high
Q – 5
Q – 10
Q
ns
ten(D)
Data bus starts being driven after STRB low (write cycle)
0
ns
tdis(D)
Data bus three-state after STRB high (write cycle)
Q + 15
Q
Q + 15
ns
td(MSC) MSC valid from CLKOUT1
–5
10
–10
0
10
ns
These values are derived from characterization data and not tested.
timing requirements over recommended operating conditions (see Note 1)
SMJ320C25-50
SMJ320C25
UNIT
MIN
MAX
MIN
MAX
UNIT
ta(A)
Access time, read data from address time (read cycle, see Notes 3 and 5)
3Q – 31
3Q – 35
ns
tsu(D)R
Setup time, data read before STRB high
17
23
ns
th(D)R
Hold time, data read from STRB high
0
ns
td(SL–R)
Delay time, READY valid after STRB low (no wait states)
Q – 20
ns
td(C2H–R)
Delay time, READY valid after CLKOUT2 high
Q – 21
Q – 20
ns
th(SL–R)
Hold time, READY after STRB low (no wait states)
Q – 1
Q + 3
ns
th(C2H–R)
Hold time, READY after CLKOUT2 high
Q – 1
Q + 3
ns
td(M–R)
Delay time, READY valid after MSC valid
2Q – 25
ns
th(M–R)
Hold time, READY after MSC valid
0
ns
NOTES:
1: 0 = 1/4tc(C)
3. A15–A0, PS, DS, IS, R/W, and BR timings are all included in timings referenced as ”address”
4. Delays between CLKOUT1 /CLKOUT2 edges and STRB edges track each other, resulting in tw(SL) and tw(SH) being 2Q with no
wait states.
5. Read data access time is defined as ta(A) = tsu(A) + tw(SL) – tsu(D)R + tr(C).
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相關代理商/技術(shù)參數(shù) |
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|---|---|
| SM320C25FJM | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:16-Bit Digital Signal Processor |
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| SM320C26BFJM | 制造商:Texas Instruments 功能描述:DSP FIX PT 16BIT 40MHZ 10MIPS 68PIN JLCC - Rail/Tube |
| SM320C26BGBM | 制造商:TI 制造商全稱:Texas Instruments 功能描述:DIGITAL SIGNAL PROCESSOR |
| SM320C2810-EP | 制造商:TI 制造商全稱:Texas Instruments 功能描述:Digital Signal Processors |
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