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參數(shù)資料
| 型號(hào)： | SM3-19.44M |
| 廠商： | Connor-Winfield |
| 文件頁數(shù)： | 18/36頁 |
| 文件大小： | 0K |
| 描述： | IC MOD TIMING 19.440MHZ STATUM 3 |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | SM3 |
| 類型： | 定時(shí)模塊，系統(tǒng)時(shí)鐘 |
| PLL： | 是 |
| 主要目的： | 以太網(wǎng)，ADM，DSLAM，SONET/SDH，Stratum，TDM |
| 輸入： | LVCMOS |
| 輸出： | LVCMOS |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 4:3 |
| 差分 - 輸入:輸出： | 無/無 |
| 頻率 - 最大： | 19.44MHz |
| 電源電壓： | 3.135 V ~ 3.465 V |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 通孔 |
| 封裝/外殼： | 32-DIP 模塊 |
| 包裝： | 管件 |
| 其它名稱： | CW642 SM3 19.44M SM319.44M |
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SM3 Data Sheet #:
TM052
Page 25 of 36 Rev: 06 Date: 01/26/11
Copyright 2011 The Connor-Winfield Corp. All Rights Reserved
Specifications subject to change without notice
Application Notes
Available Output1 frequencies are: 12.96 MHz, 19.44 MHz, 25.92 MHz, 38.88 MHz, 51.84 MHz or 77.76MHz. After the module is
powered up, pull the reset pin low for 10ms. Wait 1200ms and read the contents of register 0x33. If it reads 1 then the module came
up properly. If it reads 0 then reset the module and re-read register0c33 after 1200ms. The contents of 0x33 must read 1 before using
the module.
Reference Inputs – The application may supply up to 4 reference inputs, applied at input pins Ref1 - 4. They may each be 8
kHz, 1.544 MHz, 2.048 MHz, 12.96 MHz, 19.44 MHz, 25.92 MHz, 38.88 MHz, 51.84 MHz or 77.76 MHz. The device auto-detects the
reference frequencies, and they may be read from the Ref(1-4)_Frq_Priority registers in register control mode, as described in the
control mode sections that follow.
Reference switches are performed in a hitless manner. However, if the application externally changes the frequency of a particular
reference, the device requires 20ms to auto-detect the new frequency. Manual switches to a frequency changed reference should not
be made during this interval. Automatic reference selection mode accounts for the auto-detection in the reference qualification.
References would typically (but need not be) connected in decreasing order of usage priority. For example if redundant BITS clocks
are available, they would typically be assigned to
Ref1 and Ref2, with other transmission derived signals following thereafter.
Master/Slave operation – For some applications, reliability requirements may demand that the clock system be duplicated. The
SM3 device will support the master/slave duplicated configuration for such applications. To facilitate it’s use, the device includes the
necessary signal cross coupling and control functions. Redundancy for reliability implies two major considerations: 1) Maintaining
separate failure groups such that a failure in one group does not affect it’s mate, and 2) Physical and logical partitioning for repair,
such that a failed component can be replaced while the mate remains in service, if so desired. System design needs to account to
meet system level goals.
Master / Slave Configuration
Figure 8
STC3500
SM3G
8 kHz
M/S REF
REF4
REF1
#2
SM3G
#1
M/S REF
8 kHz
Synchronized clock output
REF1
REF4
REF1
REF4
M/S_OUT
OUTPUT1
BITS_CLK
OUTPUT1
M/S_OUT
BITS_CLK
BITS clock output
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