參數(shù)資料
型號: SLE 24C04
廠商: SIEMENS AG
元件分類: DRAM
英文描述: 4 Kbit (512 ×8 bit) Serial CMOS-EEPROM with IIC Synchronous 2-Wire Bus(4K位 (512 ×8 位)CMOS串行EEPROM(帶IIC控制))
中文描述: 4千位(512 × 8位)串行的CMOS EEPROM,帶有國際進(jìn)口同步2線巴士(4K的位(512 × 8位)的CMOS串行EEPROM的(帶控制國際進(jìn)口許可證))
文件頁數(shù): 12/23頁
文件大小: 324K
代理商: SLE 24C04
SLx 24C04
Semiconductor Group
12
1999-02-02
5
Changing of the EEPROM data is initiated by the master with the command byte CSW.
Depending on the state of the Write Protection pin WP either one byte (Byte Write) or up
to 16 bytes (Page Write) are modified in one programming procedure.
Write Operations
5.1
Byte Write
Figure 7
Byte Write Sequence
The erase/write cycle is finished latest after 8 ms. Acknowledge polling may be used for
speed enhancement in order to indicate the end of the erase/write cycle (refer to
chapter 5.3
Acknowledge Polling).
Address Setting
After a START condition the master transmits the Chip Select
Write byte CSW. The EEPROM acknowledges the CSW byte
during the ninth clock cycle. The following byte with the
EEPROM address (A0 to A7) is loaded into the address
counter of the EEPROM and acknowledged by the EEPROM.
Finally the master transmits the data byte which is also
acknowledged by the EEPROM into the internal buffer.
Then the master applies a STOP condition which starts the
internal programming procedure. The data bytes are written in
the memory location addressed in the EEA byte (A0 to A7)
and the CSW byte (A8). The programming procedure consists
of an internally timed erase/write cycle. In the first step, the
selected byte is erased to
“1”. With the next internal step, the
addressed byte is written according to the contents of the
buffer.
Transmission of Data
Programming Cycle
Command Byte
CSW
S
P
C
K
A
C
K
A
S
T
A
R
T
T
O
P
S
EEPROM Address
EEA
Data Byte
Bus Activity
Master
SDA Line
Bus Activity
EEPROM
IED02129
C
K
A
0
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SLA 24C08 8Kbit (1024 × 8 bit) Serial CMOS-EEPROM with IIC Synchronous 2-Wire Bus(8K位 (1024 × 8 位) CMOS串行EEPROM(帶IIC控制))
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